Hi, I am looking to control a H-bridge with a PWM which I have generated in my code, however I am clueless on how to include a dead timing in the PWM. I need a deadtime of 750ns on the on-time and 1us off time. The pwm generator is shown below. Thanks

module igbt_clock_gen (clock,reset,clock1,clock2,clock3,clock4); input clock,reset; output clock1, clock2, clock3, clock4; wire temp1;  freq_div f1 (clock,reset,temp1); clock_multiplier c1 (temp1,clock1,clock2,clock3,clock4); endmodule  module freq_div(clock, rst, clock_out); input clock,rst; output reg clock_out; reg [15:0] counter;  always @(posedge clock or negedge rst) begin 	if(!rst) 	begin 		counter<=16'd0; 		clock_out <= 1'b0; 	end 	else 	if(counter==16'd6667) 	begin 		counter <= 16'd0; 		clock_out <= ~clock_out; 	end 	else 	begin 		counter<=counter+1; 	end end  endmodule  module clock_multiplier (clock, clock1, clock2, clock3, clock4); input clock; output clock1, clock2, clock3, clock4;  assign clock1 = clock; assign clock2 = ~clock1; assign clock3 = clock1; assign clock4 = ~clock1;  endmodule

 

Hi, I am looking to control a H-bridge with a PWM which I have generated in my code, however I am clueless on how to include a dead timing in the PWM. I need a deadtime of 750ns on the on-time and 1us off time. The pwm generator is shown below. Thanks

module igbt_clock_gen (clock,reset,clock1,clock2,clock3,clock4); input clock,reset; output clock1, clock2, clock3, clock4; wire temp1;  freq_div f1 (clock,reset,temp1); clock_multiplier c1 (temp1,clock1,clock2,clock3,clock4); endmodule  module freq_div(clock, rst, clock_out); input clock,rst; output reg clock_out; reg [15:0] counter;  always @(posedge clock or negedge rst) begin 	if(!rst) 	begin 		counter<=16'd0; 		clock_out <= 1'b0; 	end 	else 	if(counter==16'd6667) 	begin 		counter <= 16'd0; 		clock_out <= ~clock_out; 	end 	else 	begin 		counter<=counter+1; 	end end  endmodule  module clock_multiplier (clock, clock1, clock2, clock3, clock4); input clock; output clock1, clock2, clock3, clock4;  assign clock1 = clock; assign clock2 = ~clock1; assign clock3 = clock1; assign clock4 = ~clock1;  endmodule

Newlines are nice.

The dead time is just a delay between switching states, so add some delay after going to 00, before going to anything else...