How to implement this MUX? (Verilog)

Discussion in 'Homework Help' started by jegues, Feb 19, 2011.

  1. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
    Hello all,

    I'm trying to figure out how I'm going to implement this MUX in verilog. (See figure)

    How do I implement a MUX that has 8 inputs and 8 outputs?

    See the other figure attached for my verilog code up to now.

    The one portion of my code that I'm unsure about is the case statement. Does evaluate the binary value of S? If not, how can I code it so I can make the connections of each set of inputs to each set of outputs?

    I have to write the rest of the verilog code to implement this whole schematic so I'm a little confused on how to start the main module as well.

    Any help?

    EDIT: I've attached my attempt at the "main" module for this circuit as well.
    Last edited: Feb 19, 2011
  2. Georacer


    Nov 25, 2009
    I 'm not that fluent in verilog, but I know you will find an example that will be of help in the attachment.
  3. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
    Bump, still looking for some more help
  4. narasimhan


    Dec 3, 2009
    if you are using Xilinx then when you check the syntax it will return errors if any.
    Anyway I think the case should look like
    2'd 0:
    2'd 1:
    2'd 2:
    2'd 3: