hi I m doing my masters and in my proj i just need to ge full length of my circuit diagram so in that process i wrote code in vhdl and i need to get full length diagram in that so as my code is very big i got my rtl digram to very big in 3 pages and if at all i want to get all those in a single gate level design what should be done

kindly help me as my proj dates are being completed by aug so kindly help me

 

simplify the diagram, otherwise take it to Kinkos and cut and pastee.