How to draw timing diagram from logic gates???

Thread Starter


Joined Mar 14, 2012
hi, im learing about timing diagram with propagation delay but im having a hard time understand how to draw a timing diagram from expression/logic gates.

Here is a example:

F = A + (B*C), so A is OR with (B AND C). each gate having delay of 5 NS.How do i come up with a timing diagram for this? do i first make a truth table??? i mean where should i first start to tackle problem like this? thank


Joined Oct 2, 2009
Yes, draw a truth table.
Next get some checkered or graph paper.
Draw voltage waveforms in time steps of 5ns.
Time is on the horizontal axis and volts on the vertical axis.

Draw three voltage waveforms, one each for A, B and C showing all eight possible combinations of A, B and C

Next show the waveform for (B AND C) taking into consideration a 5ns propagation delay.

Finally show the waveform for F = A + BC, again with a 5ns propagation delay.

Thread Starter


Joined Mar 14, 2012
this is a similar problem but i dont get where did they get the w to be 0 until 10 ns or how x is 1. Did they "assumed"???


Joined Jun 14, 2011
I am actually working out of the exact same book as you for my Digital Systems class. Your functions of w,x, and y are already given to you in the problem. The truth tables he is referring to are for V, and Z, V will be the truth table for W and X (since W and X are an AND gate). Z will be the output of V and Y (OR gate). Look at page 225 and it should help explain to you how to read the graph.