How to design a synchronous counter with Mulitisim?


Joined Feb 24, 2006
Let's start with some requirements.
How many bits?
Is the clock signal available?
Does it have a maximum frequency?
Can you use any type of Flip-Flop?
Are we using real parts or ideal parts?

You may wish to look for a datasheet of a 4-bit synbcronous counter such as a 74LS161 for example. There may be clues about the internal implementation.

Thread Starter


Joined Dec 2, 2006
design a synchronous counter with count sequence 1,0,4,6,10,11,12 with don't care at 13,14,15. jk flip-flops


Joined Feb 24, 2006
So you want a 4-bit syncronous counter using generic JK Flip-Flops.

When you say don't care at 13, 14, 15 do you mean that you don't care what state you go to if you are in one of those states? What do you want to do for the other unused states(2,3,5,7,8,9)?

Recomendation: It's generally a really bad thing to do nothing if the counter goes to an illegal state. The number one strategy is to ALWAYS have a transition to a valid state if you find yourself in an illegal state. If the assignment really specifies a don't care then whatever decision you make must be correct.

If it were me I'd pick state 0 as the follow state of any illegal combination. Does this help?