How to design high value capacitance capacitor using cadence

 

How to design high value capacitance capacitor using cadence

It is quite simple in theory, but difficult in practice. You make the area of the plates large, and you make the separation small. Trying to achieve practical results on a wafer is notoriously difficult. Good Luck with that.

 

It is quite simple in theory, but difficult in practice. You make the area of the plates large, and you make the separation small. Trying to achieve practical results on a wafer is notoriously difficult. Good Luck with that.

Thanksjust wanted to get into nano range with the help of pico value capacitance

 

In addition to the area of the plates you can look at a couple of other things:

1) Number of metal layers.... If the number of plates is not obvious, A transistor can have it's source and drain shorted for one plate, while the transistor gate is the other plate. That in addition to all of the available metal layers stacked on top.

2) Exploiting the fringe effect... By interdigitating the adjacent metal as well as top to bottom metal you can create a capacitor that is slightly more dense than simply alternating plates top to bottom.


"Trying to achieve practical results on a wafer is notoriously difficult " - Empirical testing .... Design a few test structures that vary by a power of two and measure them

 

Any chance that you can use NMOS transistors wired up as capacitors? We would wire-up thousands of these in parallel when I was contracting at AMD to get good bypass capacitance on voltage regulators.

Connect the source and drain of each NMOS together. Substrate is of course always connected to ground. The short between the source and drain can go anywhere as long as the transistor always remains ON. In other words, during whatever the large signal swing is, the gate voltage should always remain a threshold voltage above the voltage of the shorted source-drain.

The capacitance of each NMOS is about WL(Cox) where W, L and Cox are the transistor width, length and gate capacitance. If you wire up 5,000 of these guys, the capacitance is about 5,000WL(Cox).

In most cases, the short between the source and drain does go to ground, but it doesn't have to. What is required is that the transistor is always in an ON condition. It is the presence of electrons in the channel that provides for the simple value of capacitance, as capacitive action (displacement current) is provided by the in-rush or out-rush of channel electrons. In this case the depletion region capacitance is blocked and is not seen.

 

Any chance that you can use NMOS transistors wired up as capacitors? We would wire-up thousands of these in parallel when I was contracting at AMD to get good bypass capacitance on voltage regulators.

Connect the source and drain of each NMOS together. Substrate is of course always connected to ground. The short between the source and drain can go anywhere as long as the transistor always remains ON. In other words, during whatever the large signal swing is, the gate voltage should always remain a threshold voltage above the voltage of the shorted source-drain.

The capacitance of each NMOS is about WL(Cox) where W, L and Cox are the transistor width, length and gate capacitance. If you wire up 5,000 of these guys, the capacitance is about 5,000WL(Cox).

In most cases, the short between the source and drain does go to ground, but it doesn't have to. What is required is that the transistor is always in an ON condition. It is the presence of electrons in the channel that provides for the simple value of capacitance, as capacitive action (displacement current) is provided by the in-rush or out-rush of channel electrons. In this case the depletion region capacitance is blocked and is not seen.

As the feature size gets smaller each transistor takes less area, but you need more of them, but at least the structure is regular so putting an array of them on a die is not really a problem. Maybe the tools are even better since the last time I worked with them (ca. 1992), when we measured area in picoacres.

 

How to design high value capacitance capacitor using cadence

It depends on your process. If the aspect ratio of the metal layers is tall and narrow, sidewall capacitance with interdigitated fingers may be more economical, area wise, than gate caps.

 

My comment in #4 was indicative that you could stack a number of different options .... an NMOS (or even PMOS) cap where you are using the gate oxide as a dielectric, as well as stacked metal layers, as well as interdigitated cap fingers. When I worked at National Semiconductor, I designed and characterized such a device exploiting many different "capacitive characteristics" into one structure. Depending on the process and the available layers for example in one process we worked with, there were two gate options a high voltage and a low voltage. The structure was (Substrate - LVOXIDE - POLY1 - HVOXIDE - POLY2 - M1 - M2 - M3 - M4 - M5) where you could utilize POLY1 and POLY2 (<-GATE Metal) as separate capacitor plates and the HVOXIDE as the dielectric. The total cap would consist of one plate being (Substrate, POLY2, M2, M4) while the other plate would consist of (POLY1, M1, M3, M5) all stacked and utilized together, Separation between each metal layer was 0.6um with the exception of the OXIDE layers which were 0.3um. Each metal layer had a thickness of 0.6um ... with OXIDE and POLY having a thickness of 0.3um

 

Thanks sir for enlightening me this surely will help me

 

Although I haven't worked with them, stacked metal layers (I'll call them vertical plates) sound good. The obvious advantage is signal flexibility. Side A can go positive with respect to side B, or vice-versa, and no signal is too small. This is unlike the situation with gate oxide capacitance, where the potential of the gate plate must be at least a threshold voltage higher than the potential of the shorted source-drain plate at all times (if you want a constant value of capacitance).

Vertical plate capacitors weren't developed for no reason.

ALL parasitic transistor capacitances scale down as the process node shrinks. So gate oxide capacitance, per unit area, scales down with the process shrink.

Vertical plate capacitors also consume area. In one dimension there is the distance between the fingers multiplied by the number of fingers. In the other dimension there is the length of each finger. Additionally, all metal layers used by the vertical plate capacitor are looking at a no-fly zone around the skyscraper of the vertical cap as it sticks up above the silicon plane, but this is probably not a big deal.

Generally speaking, in a head-to-head competition in terms of capacitance per unit area, any idea how gate oxide capacitance would compare to the sidewall capacitance of vertical caps? The vertical cap probably wins, especially at smaller and smaller process nodes.

Also, I would imagine that these stacked metal layer caps have p-cells for the designer. I would imagine that the user would specify the metal layers (if these are not fixed), the number of fingers, and the finger length. Then press a button, and the total cap value is returned.

The more I think about it, the more I like vertical plate caps. Because the cap per unit area doesn't shrink and because of the signal flexibility.

 

Although I haven't worked with them, stacked metal layers (I'll call them vertical plates) sound good.

Again, it depends on the process. To cut down on inter layer capacitance, some manufacturers made the ILD thicker. I'm only familiar with process generations from one manufacturer and after about 90nm, interdigitated fingers were preferred.

 

Again, it depends on the process. To cut down on inter layer capacitance, some manufacturers made the ILD thicker. I'm only familiar with process generations from one manufacturer and after about 90nm, interdigitated fingers were preferred.

That's interesting and good to know.
Thank-you!

David

 

"...the vertical plate capacitor are looking at a no-fly zone around the skyscraper of the vertical cap as it sticks up above the silicon plane, but this is probably not a big deal..." - It's not a big deal, because during the manufacturing process there is a planarization step and density step that "normalizes" everything before the next mask layer. No, you don't route route any wires near the structure with the exception of a rare case where you might route a wire through a structure to form a transmission line, but that is a different topic and a different arbitrary use of available metal resource.

 

"...the vertical plate capacitor are looking at a no-fly zone around the skyscraper of the vertical cap as it sticks up above the silicon plane, but this is probably not a big deal..." - It's not a big deal, because during the manufacturing process there is a planarization step and density step that "normalizes" everything before the next mask layer. No, you don't route route any wires near the structure with the exception of a rare case where you might route a wire through a structure to form a transmission line, but that is a different topic and a different arbitrary use of available metal resource.

It was interesting to learn a bit more about stacked metal-layer capacitors.

Thank-you!

Best,
David