- Joined Jan 29, 2020
How to design high value capacitance capacitor using cadence
It is quite simple in theory, but difficult in practice. You make the area of the plates large, and you make the separation small. Trying to achieve practical results on a wafer is notoriously difficult. Good Luck with that.How to design high value capacitance capacitor using cadence
Thanksjust wanted to get into nano range with the help of pico value capacitanceIt is quite simple in theory, but difficult in practice. You make the area of the plates large, and you make the separation small. Trying to achieve practical results on a wafer is notoriously difficult. Good Luck with that.
As the feature size gets smaller each transistor takes less area, but you need more of them, but at least the structure is regular so putting an array of them on a die is not really a problem. Maybe the tools are even better since the last time I worked with them (ca. 1992), when we measured area in picoacres.Any chance that you can use NMOS transistors wired up as capacitors? We would wire-up thousands of these in parallel when I was contracting at AMD to get good bypass capacitance on voltage regulators.
Connect the source and drain of each NMOS together. Substrate is of course always connected to ground. The short between the source and drain can go anywhere as long as the transistor always remains ON. In other words, during whatever the large signal swing is, the gate voltage should always remain a threshold voltage above the voltage of the shorted source-drain.
The capacitance of each NMOS is about WL(Cox) where W, L and Cox are the transistor width, length and gate capacitance. If you wire up 5,000 of these guys, the capacitance is about 5,000WL(Cox).
In most cases, the short between the source and drain does go to ground, but it doesn't have to. What is required is that the transistor is always in an ON condition. It is the presence of electrons in the channel that provides for the simple value of capacitance, as capacitive action (displacement current) is provided by the in-rush or out-rush of channel electrons. In this case the depletion region capacitance is blocked and is not seen.
Again, it depends on the process. To cut down on inter layer capacitance, some manufacturers made the ILD thicker. I'm only familiar with process generations from one manufacturer and after about 90nm, interdigitated fingers were preferred.Although I haven't worked with them, stacked metal layers (I'll call them vertical plates) sound good.
That's interesting and good to know.Again, it depends on the process. To cut down on inter layer capacitance, some manufacturers made the ILD thicker. I'm only familiar with process generations from one manufacturer and after about 90nm, interdigitated fingers were preferred.
It was interesting to learn a bit more about stacked metal-layer capacitors."...the vertical plate capacitor are looking at a no-fly zone around the skyscraper of the vertical cap as it sticks up above the silicon plane, but this is probably not a big deal..." - It's not a big deal, because during the manufacturing process there is a planarization step and density step that "normalizes" everything before the next mask layer. No, you don't route route any wires near the structure with the exception of a rare case where you might route a wire through a structure to form a transmission line, but that is a different topic and a different arbitrary use of available metal resource.
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