# How to delay a clock signal?

Discussion in 'General Electronics Chat' started by Ordos, Mar 12, 2008.

1. ### Ordos Thread Starter New Member

Mar 12, 2008
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Hello everyone!

Does anyone has an idea of how I could delay a given clock signal by half the period?
At the end, I need to have both clock signal (with the same frequency), only that the second one starts half a period later? (see attached picture [1])

Regards,
Ordos

[1] http://b.imagehost.org/view/0243/clock_delay.jpg

2. ### KMoffett AAC Fanatic!

Dec 19, 2007
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Can you just use an inverter? Or is the condition of both signals being zero to start with (as in your diagram) important?

Ken

3. ### mik3 Senior Member

Feb 4, 2008
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search on google for pulse delay with logic gates or with op-amp

4. ### Ordos Thread Starter New Member

Mar 12, 2008
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They need to be zero at the beginning...

Unfortunately, the search didn't return any helpful pages...

5. ### beenthere Retired Moderator

Apr 20, 2004
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It's easy with some logic, like a NOR gate in addition to the inverter (you can use a section of the NOR for that). Easy, that is, if this is a logic signal and you can also provide a run signal to control the NOR gates.

One important question is how tight is the timing between the clock and the quadrature clock? If you can live with the 10's of nanoseconds delay through the inverter, fine. If not, then some compensating delay will have to be found for the original clock to adjust the timing.

6. ### KMoffett AAC Fanatic!

Dec 19, 2007
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Does the delayed clock put out one more pulse after the last primary clock pulse? And are these logic (ttl or cmos) signals? And is the primary clock a fixed frequency?

Ken

7. ### Ordos Thread Starter New Member

Mar 12, 2008
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Strange as it may seem, it turned to work only with the inverter, as suggested by KMoffett! Both signals start at LOW.

I'm not quite sure about the delay through the inverter. I'm doing a FPGA design and in the simulation it does look fine...

It is actually quite wired, because I'm inverting already a delayed signal (by 180 grad; I get it from the Digital Clock Management of Xilinx). With these both signals I'm feeding two identical logic blocks which count until 500 (16bit counter + comparator). If I don't use the inverter, but only the signal delayed by 180 grad, the output of the one counter is delayed only by 1/4 of the period in comparison to the other...
By using the inverter, it get's OK...

Yes, it does, but it is OK. These are two identical counters which I supply with the both clock signals. The second counter should just start counting one period later.

This is actually a FPGA design (schematic based). At the end everything should be burned on the FPGA.

8. ### scubasteve_911 AAC Fanatic!

Dec 27, 2007
1,202
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Orods, what sort of FPGA are you using? Most of the time there is a clock manager resource available that can do all sorts of great stuff with your clock signals, including accurate phase delays and frequency division/multiplication whilst holding a 50/50 duty.

Pretty much every recent Xilinx FPGA has these resources available.

Steve

9. ### Ordos Thread Starter New Member

Mar 12, 2008
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Well, I'm using the Virtex II Pro.
You mean the DCM - Digital Clock Management, dont' you?

10. ### raffter Active Member

Feb 28, 2008
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how about a phase shift circuit....

Ralph