How to create delay in Multisim 7?

Thread Starter


Joined Dec 7, 2012
Hello forum

The task is to generate these signals in this order:

Rich (BB code):
Q3 Q2 Q1
0  0  0
0  0  1
0  1  0
0  1  1
1  0  0
and then this should repeate endlessly.
I am stuck, the output is all 0's. The trigger (T_FF) works on a separate circuit, but not here.

I guess this happens because when the signals pass through "AND" and "OR" elements, they are delayed a bit from clock signal, which comes directly, and thus doesn't flip the trigger. I have trouble finding an element which can delay the clock signal for a few milliseconds.

See the full circuit in multisim 7 format in attachments.

and the screenshot just in case:

Any help appreciated.

Also my university uses multisim 7, so other software won't help.


Thread Starter


Joined Dec 7, 2012
It appears you want a three bit counter.
Yes, exactly. This circuit should serve as a controller for 3 others, which I managed to get working. I'll attach a decoder at the output of this circuit which will control those 3.

Here's the assignment text (hope my translation skills are enough)

Analysis, synthesis and simulation of sequential circuit

1) yi = Vi τs*fm = τ0*f1 v τ2*f2 v τ4*(f3<binary +>f1) v τ6*f1

y1 = f1(x1, x2, x3, x4) = V1 (0, 1, 3, 6, 8, 9, 12, 13, 15)

y2 = f2(x1, x2, x3, x4) = V1 (2, 4, 7, 9, 11, 13)

y3 = f3(x1, x2, x3, x4) = V1 (0, 2, 5, 8, 10, 12, 15)

Where V or v is a plus sign.

2) Table of states:

x k |0|1|1|1|1|1|1|1|1|...

That's all it says. Here's what I have done so far:

Minimalised the f1, f2, f3 functions and made circuits, here's f1 for example:, and it's output:
Then synthesed and minimalised the controller, which is in original post, but it doesn't work and I am stuck.