Hi all,

Shall we connect the single-ended SCK (Serial Clock) pin of ADC to the P-side of the differential pin pair of the FPGA (If there is no Clock pins are available, I mean if all clock pins are used)?. If so, then, what should I do with the N-side of the differential pin of FPGA?, Is this (N-Side) pin should connect to the GND or left un-connected?.

 

Hi all,

Shall we connect the single-ended SCK (Serial Clock) pin of ADC to the P-side of the differential pin pair of the FPGA (If there is no Clock pins are available, I mean if all clock pins are used)?. If so, then, what should I do with the N-side of the differential pin of FPGA?, Is this (N-Side) pin should connect to the GND or left un-connected?.

Hello,
could you please give the part number (the ADC IC). The SCK pin is "input" or "output" for ADC? In case when "SCK" is input pin for ADC, I suppose that you can use any I/O pin of FPGA, otherwise not.

Best Regards

 

Hello,
could you please give the part number (the ADC IC). The SCK pin is "input" or "output" for ADC? In case when "SCK" is input pin for ADC, I suppose that you can use any I/O pin of FPGA, otherwise not.

Best Regards

Hi FlyingDutch,

XCZU5EG
Zynq UltraScale+ Device Technical Reference Manual

The clock signal for Input and Output of ADC. Please could you check above manual and tell me.