Hi All,

As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field so my question is particularly related to the IC fabrication. In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

 

You aren't really understanding what it means for the energy of electric current to be in the E and B fields around the conductors. It has no practical effect on ESD protection. All of the normal measures to limit ESD are completely effective on the scale of IC internals.

 

You aren't really understanding what it means for the energy of electric current to be in the E and B fields around the conductors. It has no practical effect on ESD protection. All of the normal measures to limit ESD are completely effective on the scale of IC internals.

Hey mate can you please elaborate more, Thanks

 

Maybe you can explain why you think the scale changes anything.

Keep in mind, you need electrical potential between objects for current to flow. That is, you need a difference in charge.

If things are equipotential there can be no flow of current. Even if you would measure a million volts between you and some object, unless you get within the range where the resistance between you and the object is low enough for current to flow, nothing will happen.

That’s how birds can sit on live power lines—there is a 0V difference between them and line. If there is a 0V or very low voltage difference between a device and the person or machine handling it, it doesn’t matter if it would appear highly charged to something else. That is the basis for ESD protection, equalizing voltages relative to each other.

This is referenced to ground, but the ground could have a substantial charge compared to ungrounded things, yet it makes no difference if you, the machines, and the wafer are equipotential. Eliminating potential difference caused by things like triboelectric effects (for example, pulling tape off a package) is a matter of constant contact with the 0V point (the grounded wrist strap, the grounded, conductive surfaces of furnature, etc.).

This equalizes the potential charge by absorbing differences into the large charge sink represented by the grounding system rather than through the sensitive parts to ground.

 

Congratulations Ya'akov. You have wonderfully explained a convoluted and quite confusing question.

 

Funny, but I could have sworn the OP was asking about EMI not ESD.

 

In IC fabrication, the entire die is at earth potential. There are no induced electrical fields that can disrupt the process.

 

In IC fabrication, the entire die is at earth potential. There are no induced electrical fields that can disrupt the process.

Not exactly true. During the fabrication process accelerated charge in the form of ions (doping, advanced chip processing uses implantation instead of diffusion for precise dopant control) can be implanted into the surface, bulk and buried regions of the die. This charge often hits parts of the die that are insulated from the grounded substrate causing those layers to charge to process destructive levels unless countermeasures are used that neutralize that charge.

https://pubs.aip.org/aip/rsi/articl...a-flood-gun-for-wafer?redirectedFrom=fulltext

In modern ion implanters, a plasma flood gun (PFG) is used to neutralize wafer charge during the doping process, preventing the breakdown of floating wafers caused by the space charge accumulation. Typically, there are two kinds of PFGs, namely, dc arc discharge with filament and RF discharge.

 

In IC fabrication, the entire die is at earth potential. There are no induced electrical fields that can disrupt the process.

Oh, very much not the case!

Many of the processing steps in IC fabrication involve a LOT of strong E&M fields -- ion implantation and plasma etching just to name a couple.

Every piece of conductor on the die acts like an antenna and develops a voltage differential in response. The transistor gates in deep submicron processes are very sensitive to being blown if there is more than a few volts across them. So fabs have developed antenna rules which limit the area of isolated conductor that can be connected to a transistor's gate at any point in the fabrication process. Designers have to ensure that conductors that will exceed that limit have a path to the substrate through a diode connection before the processing step that will create that over-limit area. If you ignore this, you are practically guaranteed to end up with a worthless die with a bunch of blown gates.

 

Isn’t there a path created to the substrate?

 

Hey guys I am not talking about the fabrication process but the circuit layout

 

Isn’t there a path created to the substrate?

What path? Say you have a Metal 1 line connected to the polysilicon that forms the transistor gates of the input of a logic device in the bottom-left corner of the die. Perhaps this input will eventually connect to the output of a logic gate that is located in the upper-right corner of the die. So the Metal 1 runs vertically the height of the chip, then jumps up to Metal 2 to cross horizontally across the chip and then back down to Metal 1 and then down to the source/drain regions of the output transistors of the driving gate. But after Metal 1 is laid down and etched, all you have is a long line of metal connected to a couple of transistor gates and it acts like an antenna with no place to dump the energy except into the most vulnerable region available at that time, which are the gates. So there is a limit on how much Metal 1 can be connected to an unprotected gate.

So how do you protect the gate?

You make your long metal line in two pieces -- a short one connected to the gate and a long one that runs the length. You then make contacts to an implant region in the substrate that will result in a reverse-biased diode to the substrate during normal operation. This connection becomes the point where inducted currents can make it to the substrate from that point on. Then you connect the two pieces of Metal 1 with a short jumper of Metal 2 later in the processing.

Does this add complexity to the design? Yes.

Does this add additional potential points of failure to the circuit? Yes.

Does this add undesired parasitics to the circuit? Yes.

These are just prices that must be paid in order to get the chip to yield.

 

Hey guys I am not talking about the fabrication process but the circuit layout

Everything interferes with everything. The issue is how to minimize it to a degree that is acceptable.

Just as there are layout techniques to minimize crosstalk and other EMI issues in everything from overhead power lines to PCBs, there are layout techniques to minimize these issues in IC design. Those techniques are somewhat different for different process scales, just like the techniques are somewhat different for large-component PCBs relative to find-pitch SMT-component PCBs.

 

Hi All,

As i recently came to know that the energy is not travelled in the wire infect it is travelled in the space around the wire in the electrical and magnetic field so my question is particularly related to the IC fabrication. In IC fabrication we have micro-scale deployment of transistors and wire connections. On a single dice which is smaller than the palm has millions of transistors, so it means that the these connections and transistors have very close space to each other so at such small scale if the energy is delivered in space then it means that this energy must have interfered with the other metal connections energy so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

To answer basic question, you premise is wrong, slightly , when you say " neither interfere or degraded "
the key is that a "transmiter" must cause a low enough amount of "interference" such that the "receiver" is not "interfered" with outside the constraints.

So in digital design, the routes are fairly low impedance, and the receivers have a threshold effect, so that any "interference" below the receivers threshold is "irrelevant" as it will not cause a "disturbance" of the output .
In analog, the effect is different, and broad band, and is relevant to signal to noise ratio effects, but true differential analog circuitry on chip is very effective at noise suppression,

Also remember your field theory, and the effect that a "wire" above a "plane" has.

At the end of the day,
for chips as for PCBs ,the tools are great at being able to predict Maxwell field equations and the effects on conductors/circuits.

 

so how they are able to maintain the isolation and make sure the electric and magnetic field neither interfere or degraded ?

shrinking structures does have challenges which is why things started with more manageable sizes (in this case early structures were MUCH larger) and then things are gradually refined and optimized along the way through a series of refinements.
you cannot break laws of physics. new products are designed based on existing knowledge and then - tested. if the tests fail, you do not have viable product or at best you need to de-rate its specs so that at least it can operate at lower performance level. or you give up... or go back to the drawing board and redesign. you could also wait until the next manufacturing process is available that does not have the same limitations.

 

Layers are built, destroyed and their crystalline structures broken and restructured many times during the bare wafer to finished die process. Hitting an oxide layer with several MeV energy particles to dope layers underneath requires thermal annealing to rebuild the semiconductor structures. The trick is to do this with precision and repeatability so all of the side-effects can be accounted for, adjusted for and controlled within process limits. It's a never ending fight with the demons of failure.
https://www.hzdr.de/db/Cms?pOid=10921&pNid=0

 

Hey guys I am not talking about the fabrication process but the circuit layout

Yet the thread is entitled, "How EMI is handled in IC fabrication process?"

Do you see how people might think you are asking how EMI is handled in the IC fabrication process?

Perhaps a better title would have been something like, "How is EMI handled in IC layout?"

 

Yet the thread is entitled, "How EMI is handled in IC fabrication process?"

Do you see how people might think you are asking how EMI is handled in the IC fabrication process?

Perhaps a better title would have been something like, "How is EMI handled in IC layout?"

my bad mate

 

You make your long metal line in two pieces -- a short one connected to the gate and a long one that runs the length. You then make contacts to an implant region in the substrate that will result in a reverse-biased diode to the substrate during normal operation. This connection becomes the point where inducted currents can make it to the substrate from that point on. Then you connect the two pieces of Metal 1 with a short jumper of Metal 2 later in the processing.

Reverse biased diodes stopped working for us at around 130nm when the gate oxide broke down before the diode. We had to start using something we called gated NAC diodes, which were transistors with the gate and source grounded and the drain connected to the antenna.

 

Hey guys I am not talking about the fabrication process but the circuit layout

Then why is this the title of the thread? And why is it in the IC Design sub-forum?