I have uploaded a circuit diagram of my counter circuit.
Could someone explain to me how the RC oscillator with the Schmit NAND gate works please?

Thank you for your time,

Rob

 

Originally posted by Hurdy@Mar 3 2006, 01:25 PM
I have uploaded a circuit diagram of my counter circuit.
Could someone explain to me how the RC oscillator with the Schmit NAND gate works please?

Thank you for your time,

Rob

[post=14575]Quoted post[/post]​

Initial fact: A schmitt trigger gate has two logic thresholds. They are refered to as the upper threshold point(UTP) and the lower threshold point(LTP). Starting from ground you must go above the UTP to get the gate to switch. After doing that you must go below the LTP to get the gate to switch back. Clear?


OK now start with an assumption: The voltage on the capacitor is 0VDC.
That leads to: The output of the gate is at Vcc because its an inverter.
If the output of the gate is at Vcc, then the capacitor is being charged through the resistor to Vcc.
Question: will it ever get there?
Answer: No
When the capacitor reaches the upper threshold voltage of the logic gate, the gate will switch back to ground.
Now the capacitor is discharging toward ground. Will it ever get there?
No, because when the capacitor discharges to the lower threshold point the gate will switch back to Vcc

and so proceed ad infinitum...

 

Thank you my friend. Your description is as how I thought it works but I didn't take into consideration + and - thresholds, which now you have described to me makes more sense on how it works.

Appreciate it a lot.

Thanks again,

Rob

 

Hi again,

For this assignment I have been asked the question 'how is the counter enabled?'.

Do you think the question is how does the circuit count etc, or are they asking me how it initially starts up?

Also another question I have been asked is 'How and when is the counter reset?'.

I understand the idea of the RC oscillator, but this time the voltage to the capacitor is constant. Will the capacitor once at its maximum storage then automatically discharge its contents exponentially? Therefore resetting the counter on every capacitor discharge once the capacitor falls below the LTP of the Schmitt gate.

OR will the circuit only reset at start-up until the capacitor charges to the UTP of the Schmitt gate ensuring that the count is reset back to 0 for the first clock count?

 

I've just checked the simulation with a scope and found the the voltage at the left RC is constant high.

So from what I know about capacitors is that they dont allow DC voltage to pass through them. But initialy as the capacitor charges for the first time the voltage is less than the UTP required by the Schmitt gate. This will then place a '1' on the reset therefore making the counter reset to count 0. Once the capactior is charged beyond the point of the UTP the Schmitt gate will output a 0 therefore dropping the reset state and the counter can then count on each rising clock pulse.

So if I have this correct I think I have just answered my reset question.

 

Ok I have another question.

It says the frequency of the relaxation oscillator is calculated by the formula

f = 1 / KCR

Calculate the value of K.

What does K stand for?

C = 1uF
R = 850K ohm

 

Originally posted by Hurdy@Mar 5 2006, 12:47 PM
Ok I have another question.

It says the frequency of the relaxation oscillator is calculated by the formula

f = 1 / KCR

Calculate the value of K.

What does K stand for?

C = 1uF
R = 850K ohm

[post=14687]Quoted post[/post]​

I'm going out on a small limb here, but I think K is a constant that depends on the LTP and the UTP.

The charging equation for for an RC circuit is

V = Vcc*(1 - exp(-t/RC)) for all t >= 0; V=0 at t = 0

solving for t we get

t = -RC*ln(1 - (V/Vcc))

We want to solve for two values of t. The first (t1) is when V = LTP, and the second (t2) is when t = UTP.

The discharge equation is

V = Vo*exp(-t/RC) for all t >= 0; Vo is the initial condition at t = 0.

Note we have reset our absolute time scale back to zero here

solving for t we get (t3)

t3 = -RC*ln(V/Vo), with Vo = UTP and V = LTP

The period (P) is then

P = t3 + (t2 - t1)

and the frequency is 1/P

This should lead to a value of K for this type (4000 series CMOS) of gate. If you do this experiment with another type of gate or even another 4000 series gate you might get different results.