How do you make a 2-bit Synchronous down counter using D type flip flop?

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Dntk1

Joined Dec 31, 2012
3
This sounds oddly like a homework problem....

So I'll ask you, what have you done to solve this?
Ive been able to determine the present and the next states where the present states are

00
01
10
11

Where the next states will be

11
00
01
10

for the sequence 3210
 

MrChips

Joined Oct 2, 2009
21,880
You can do this with Karnaugh mapping or you can do this intuitively.
Ask yourself, under what condition of the D-input does the D-type flip-flop go high?
 

WBahn

Joined Mar 31, 2012
26,156
Ive been able to determine the present and the next states where the present states are

00
01
10
11

Where the next states will be

11
00
01
10

for the sequence 3210
So put this information into a single table.

Q1|Q0||Q1n|Q0n
0|0||1|1 (typo fixed - Q0n was 0 before)
0|1||0|0
1|0||0|1
1|1||1|0

Now extend the table with excitation values (for each FF, call these D1 and D0). Hint, for a DFF, thisi is trivial).

Then determine the logic equation (or gates) that will take you from the current state outputs to the next state inputs for each DFF.
 
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