How do I do this logic : CMOS

Thread Starter

simeonz11

Joined Apr 29, 2008
98
I wish to do this , working with cmos , under 100 khz .

I need pointers , I am trying to improvise something on a piece of paper but I am simply braindead .

I need pointers . I want the starting edge of signal 2 to cut off the signal .

Plz delete the thread : plz help before I kill myself , this is the new thread .
 

Attachments

t_n_k

Joined Mar 6, 2009
5,448
Try a D flip-flop like the HEF4013. Feed pin2 to pin5. Use signal 1 as the clock input pin 3 and signal 2 as the reset [CD] pin 4. Put pin5 to ground. Output on pin 1.

Something like that anyway.
 

t_n_k

Joined Mar 6, 2009
5,448
A mistake in previous post. Put pin 6 [SD] to ground rather than pin 5.

Also, since only half the HEF4013 is required - ground all unused input pins on second flip-flop.
 

Thread Starter

simeonz11

Joined Apr 29, 2008
98
thx very much tnk .

I actually solved my problem on my own this morning .

this is how I solved it , old fashion way.
 

Attachments

SgtWookie

Joined Jul 17, 2007
22,201
I actually solved my problem on my own this morning .

this is how I solved it , old fashion way.
Your schematic will not result in the desired output as it's drawn.

TNK's suggestion will work just fine, as long as the 1st cycle is not important.
 
Last edited:

Thread Starter

simeonz11

Joined Apr 29, 2008
98
that last most right gate is a xor gate

so what exactly is tnk's drawing .

5 or 6 on the ground ?

Plz be specific , I'm about go go buy one of these things .
 

SgtWookie

Joined Jul 17, 2007
22,201
6 to ground. 2 wired to 5.
Also ground 8,9,10,11 (unused inputs)

The very 1st output won't be correct in tnk's circuit until signal 2 goes high for a moment. After that, it'll be correct.

Your modified circuit (rightmost gate changed to an XOR) will work all of the time, but requires 3 IC's. If you're running at a fairly high frequency, propagation delays may cause you problems.

[eta]
More detail on the CD4013 pin connections:
1 - Signal out.
2 - pin 5
3 - your signal #1 input
4 - your signal #2 input
5 - (connected to pin 2)
6 - ground
7 - ground (supply pin)
8 - ground
9 - ground
10 - ground
11 - ground
12 - n/c
13 - n/c
14 - Vdd (+voltage supply)
Use a 0.1uF (100nF) capacitor across pins 7 and 14.
 
Last edited:

Thread Starter

simeonz11

Joined Apr 29, 2008
98
http://img376.imageshack.us/img376/8844/wookie.jpg

This is what I'm doing , I'm doing thius to control the phase delay of something , a comparator latches on to the desired level and I use that in a t flip flop to get a 50/50 pulse . Yes , this is an incredibly bitchy circuit and must be used with very low leak caps , and must be in a faraday cage and perhaps on a pcb .

But I need this to be almost always on for my purpose , so I must use absolute minimum duty cycle for a real ramp wave with no off time ( exept for the cap discharge )

so that image is basicly just to keep my duty cycle really low , then the cap discharges totally signal 2 gets on .

My 1st question to you is the following ..

Is this 4013 logic good for my purpose, you mentionned something about the first cycle ? will the 4013 logic work for me ?

My 2nd question is the following .

I am using cmos chip to drive my transistor , very low amps , I tried using a darlington pair with 2 x 2n4401 , but for some reason there is a massive distorted drop time dur to some parasitic capacitance , I dont understand this ad theres alot of space between the legs of both transistors .

When I use my cmos alone to drive the transistor , the switching is not clean and I get distortion everywhere .

When I use my 555 timer to do the pulsing , I use about 50 mA , and the ramp circuit JUST DONT TURN ON @ ALL . Is this because its not allowed to have higher current on base than on collector ?

Should I use a bc517 or not ? I wish to saturate this tansistor to get a fast cap discharge .

Perhaps a mosfet driver to drive my transistor ?

what do you suggest ?
 

Attachments

SgtWookie

Joined Jul 17, 2007
22,201


This is what I'm doing , I'm doing this to control the phase delay of something , a comparator latches on to the desired level and I use that in a t flip flop to get a 50/50 pulse. Yes, this is an incredibly **** finicky circuit and must be used with very low leak caps , and must be in a Faraday cage and perhaps on a PCB.
I still don't quite get what you're doing here.
Note that this is a family-type forum; please keep language squeaky-clean.

But I need this to be almost always on for my purpose , so I must use absolute minimum duty cycle for a real ramp wave with no off time (except for the cap discharge.)

So that image is basically just to keep my duty cycle really low, then the cap discharges totally (when) signal 2 (turns) on.

My 1st question to you is the following ..

Is this 4013 logic good for my purpose, you mentioned something about the first cycle?
When the power is first applied to the 4013, it won't be in a known state. In a simulation, the first output pulse is a very short duration.

Will the 4013 logic work for me?
It would need to be initialized. One way to do that would be to put a small cap to Vcc/Vdd on the SET input pin and a 10k resistor from SET to ground, instead of simply grounding the SET input. That way when power is applied, the SET input will momentarily be pulled high, establishing a known state for the 4013. However, if the application of power is slow, the pin may not be held high long enough to initialize the 4013 properly. If the cap to Vcc/Vdd is too large, the 4013 won't respond to other inputs until the cap becomes discharged.

My 2nd question is the following .

I am using the cmos chip to drive my transistor, very low current, I tried using a darlington pair with 2 x 2n4401, but for some reason there is a massive distorted drop time due to some parasitic capacitance, I dont understand this and there's a lot of space between the legs of both transistors.
4000 series CMOS ICs do have a low current source/sink capability. Even with a Vdd of 12v, sourcing or sinking 4mA is rather a stretch.

Once you get a transistor into saturation, it can take a long time to get it out of saturation. If you have two transistors in a Darlington configuration and you're saturating both transistors, you could have a long wait for them to turn off.

When I use my cmos alone to drive the transistor , the switching is not clean and I get distortion everywhere.
What is your Vdd? What resistor are you using between the CMOS output and the transistor's base?

When I use my 555 timer to do the pulsing , I use about 50 mA , and the ramp circuit JUST DONT TURN ON @ ALL . Is this because its not allowed to have higher current on base than on collector ?
Post the circuit as an image attachment.

Should I use a bc517 or not? I wish to saturate this transistor to get a fast cap discharge.
If you get the transistor deeply saturated, it'll take a long time to turn off.

what do you suggest ?
Post an image of your circuit as an attachment, preferably in .PNG format, as it will be compact and not "lossy" like .jpg images are.
 

SgtWookie

Joined Jul 17, 2007
22,201
Have you considered using an SCR to drain the cap?

Sensitive SCRs don't take much to trigger them, and they will then stay conducting until the current through them falls below a threshold level, whereupon they turn off.
 

Thread Starter

simeonz11

Joined Apr 29, 2008
98
from my cmos chip to my transistor I was using a 10k ohm

@ about 12 volts

I need a transistor that can saturate and de-saturate quickly .

I need it to let enough amps to discharge a cap quickly .

I wont be uding anything large than .01 uF
 

Thread Starter

simeonz11

Joined Apr 29, 2008
98
I didnt think of using a scr. But will it be fast enough ??

The cap will have like 1 amp @ that initial condition , maybe more .

amp in initial condition when full is = to CV/CR

but I will probably put a rtesistance there , it dont need to be super instataneous .
 
Last edited:

SgtWookie

Joined Jul 17, 2007
22,201
There are LOTS of different SCRs. I have no clue how fast you expect this thing to operate. You'll of course need to limit peak discharge current somewhat, but average power dissipation will be quite low.
 

Thread Starter

simeonz11

Joined Apr 29, 2008
98
It would need to be initialized. One way to do that would be to put a small cap to Vcc/Vdd on the SET input pin and a 10k resistor from SET to ground, instead of simply grounding the SET input. That way when power is applied, the SET input will momentarily be pulled high, establishing a known state for the 4013. However, if the application of power is slow, the pin may not be held high long enough to initialize the 4013 properly. If the cap to Vcc/Vdd is too large, the 4013 won't respond to other inputs until the cap becomes discharged.
Sgt Wookie

Plz explain this and how to make this solve my problem as bets as possible , in a very simple noob like way so I and everybody can understand .

pins pins pins .

thx
 
Top