How capacitor is used as level shifter in following datasheet.
- Thread starter aamirali
- Start date
This is, roughly, what is known as a "flying-capacitor charge pump".
Say I have a logic output from a chip that can go between 0V and 5V. But what I need is a signal that goes from 20V to 25V.
What happens if I charge a capacitor to 20V and connect one end to the logic output and leave the other dangling (the point being that it can't discharge)? Well, the dangling end of the capacitor is always 20V higher than the side connected to the other circuit, so as the logic signal goes between 0V and 5V, the dangling end goes between 20V and 25V just like we wanted. Since we aren't going to leave it dangling much longer, let's call this the high-side of the capacitor.
So now let's say we have an NFET whose source pin is at 20V and that requires a Vgs (gate-source voltage) of 3V to turn on. In theory, we can use our low logic signal signal to directly turn on and off this transistor even though every node in it is at 20V or greater.
Well, that sounds find, but as soon as we try to use that higher voltage for anything, we start drawing off charge, through leakage if nothing else, and its voltage starts dropping. So how do we get (and keep) the necessary charge on the capacitor?
Well, that depends on the waveform and the components and a few other things, but in this case consider that our logic is normally going to be LO and under those conditions we want the transistor we are controling (which we'll assume is an NFET) to be off. When it goes HI, we aren't going to keep it HI very long; in fact, we either want or are willing to let the NFET automatically turned off after a short amount of time even if we keep the logic output HI.
So, in addition to being tied to the gate, we also tie the high-side of our capacitor to the transistor source node through a resistor. Any time the logic output remains unchanged for any length of time (determined by the RC time constant, which for the values given in the data sheet would be about 66µs), the high-side voltage will settle to the source node voltage, 20V in our case, turning the transistor off. But now when the logic output transitions from LO to HI, the low-side of the capacitor quickly moves upward by 5V and since the voltage across a capacitor can't change instantaneously, the high side of the capacitor must also go up 5V from 20V to 25V, thus turning on the transistor. But it immediately starts discharging back toward 20V.
When we later take the logic input back LO, then the high side will drop by 5V taking the gate from 20V to 15V. While this will definitely keep the transistor turned off, the transistor might not like have this much negative Vgs. If it can tolerate it, we can just live with it. If we can't, we can use snubber (or clamping) diodes that clamp the voltage to only one diode drop below Vgs by providing a low impedance path to dump charge back into the capacitor. and we tie the dangling on for just a short amount of time put a capacitor on the output. The circuit shown in the diode would appear to not need the clamping diodes.
So much for that.
At first, I assumed you were asking about how the main functionality was achieved, so I wrote the following before I realized you were actually asking something different. But, perhaps this might also be useful.
Examine Section 4 starting on page 7.
Basically, between each cell an inductor is tapped off and the far side of this inductor is connected, through two transistor switches, to the other sides of both batteries. If the circuit for the top battery is turned on first, then the inductor charges pulling current from the top battery. If the switches are now reversed, this current, which has to continue flowing in the same direction, flows into the lower cell. If you close the lower switch first, then the current is flowing out of the lower cell and, when the switches are reversed, must now flow into the top cell. So, through it acts as a current pump that can move charge in either direction depending on the order in which you turn on the transistors.
Say I have a logic output from a chip that can go between 0V and 5V. But what I need is a signal that goes from 20V to 25V.
What happens if I charge a capacitor to 20V and connect one end to the logic output and leave the other dangling (the point being that it can't discharge)? Well, the dangling end of the capacitor is always 20V higher than the side connected to the other circuit, so as the logic signal goes between 0V and 5V, the dangling end goes between 20V and 25V just like we wanted. Since we aren't going to leave it dangling much longer, let's call this the high-side of the capacitor.
So now let's say we have an NFET whose source pin is at 20V and that requires a Vgs (gate-source voltage) of 3V to turn on. In theory, we can use our low logic signal signal to directly turn on and off this transistor even though every node in it is at 20V or greater.
Well, that sounds find, but as soon as we try to use that higher voltage for anything, we start drawing off charge, through leakage if nothing else, and its voltage starts dropping. So how do we get (and keep) the necessary charge on the capacitor?
Well, that depends on the waveform and the components and a few other things, but in this case consider that our logic is normally going to be LO and under those conditions we want the transistor we are controling (which we'll assume is an NFET) to be off. When it goes HI, we aren't going to keep it HI very long; in fact, we either want or are willing to let the NFET automatically turned off after a short amount of time even if we keep the logic output HI.
So, in addition to being tied to the gate, we also tie the high-side of our capacitor to the transistor source node through a resistor. Any time the logic output remains unchanged for any length of time (determined by the RC time constant, which for the values given in the data sheet would be about 66µs), the high-side voltage will settle to the source node voltage, 20V in our case, turning the transistor off. But now when the logic output transitions from LO to HI, the low-side of the capacitor quickly moves upward by 5V and since the voltage across a capacitor can't change instantaneously, the high side of the capacitor must also go up 5V from 20V to 25V, thus turning on the transistor. But it immediately starts discharging back toward 20V.
When we later take the logic input back LO, then the high side will drop by 5V taking the gate from 20V to 15V. While this will definitely keep the transistor turned off, the transistor might not like have this much negative Vgs. If it can tolerate it, we can just live with it. If we can't, we can use snubber (or clamping) diodes that clamp the voltage to only one diode drop below Vgs by providing a low impedance path to dump charge back into the capacitor. and we tie the dangling on for just a short amount of time put a capacitor on the output. The circuit shown in the diode would appear to not need the clamping diodes.
So much for that.
At first, I assumed you were asking about how the main functionality was achieved, so I wrote the following before I realized you were actually asking something different. But, perhaps this might also be useful.
Examine Section 4 starting on page 7.
Basically, between each cell an inductor is tapped off and the far side of this inductor is connected, through two transistor switches, to the other sides of both batteries. If the circuit for the top battery is turned on first, then the inductor charges pulling current from the top battery. If the switches are now reversed, this current, which has to continue flowing in the same direction, flows into the lower cell. If you close the lower switch first, then the current is flowing out of the lower cell and, when the switches are reversed, must now flow into the top cell. So, through it acts as a current pump that can move charge in either direction depending on the order in which you turn on the transistors.
Hi sry I didn't complete my question. I thnk rest of part i got deleted
I have attached one pdf file, of same circuit implementation, there they show hoe two devices communicate wih each other.
On page 2 in pdf, capacitor C73 is placed between two devices to communicate with devices having two different VCC & Gnd levels. i don't know how they have done it, or what's basic concept.
Also on PLAN point I measured volatge without C46, voltage is 7.4V.
But as soon as C46 is connected, voltage at PLAN shift to 9.40v.
I have attached one pdf file, of same circuit implementation, there they show hoe two devices communicate wih each other.
On page 2 in pdf, capacitor C73 is placed between two devices to communicate with devices having two different VCC & Gnd levels. i don't know how they have done it, or what's basic concept.
Also on PLAN point I measured volatge without C46, voltage is 7.4V.
But as soon as C46 is connected, voltage at PLAN shift to 9.40v.
My guess is that the part has the necessary reference circuitry for the SDI pin internally. Remember, these parts are specifically designed for charge pumping from difference voltage domains.
The basic concept involved is the same. The voltage on a capacitor cannot change instantaneously. So if you make a quick change in the voltage on one side using a strong driver, you make the same quick change in the voltage on the other. On the side receiving side, you need to establish a reference voltage that is maintainable. A common way of doing this is to use a much weaker driver so that the capacitor is slowly driven back to the reference level. Another way is to use a diode that rapidly replenishes the charge when the voltage is returned to its normal level and tries to go beyond it be more than a diode drop.
The basic concept involved is the same. The voltage on a capacitor cannot change instantaneously. So if you make a quick change in the voltage on one side using a strong driver, you make the same quick change in the voltage on the other. On the side receiving side, you need to establish a reference voltage that is maintainable. A common way of doing this is to use a much weaker driver so that the capacitor is slowly driven back to the reference level. Another way is to use a diode that rapidly replenishes the charge when the voltage is returned to its normal level and tries to go beyond it be more than a diode drop.
