I'm mainly a software guy, with enough hardware prototyping experience to be dangerous I have an application I'm working on where I want to clock in serial data from a device at 4 Mb/s. I tried adding a shift register in, but I still get 4,000,000 / 8 interrupts per second to my poor little Coldfire cpu.
I'd like to incorporate a deep fifo in the mix so I can go out and read in a bunch of data once in awhile via dma on my data bus or whatever. Something like a "Serial to parallel fifo", like the IDT72142 would be pure gold, but it's obsolete, probably because everyone uses FPGAs nowadays. Does anyone know of a good way to clock serial data into a fifo, then pull it out in parallel (8 or 16 bit)? I was thinking about doing an FPGA, but I'd like to just drop in an IC and get this done.
Thanks !
I'd like to incorporate a deep fifo in the mix so I can go out and read in a bunch of data once in awhile via dma on my data bus or whatever. Something like a "Serial to parallel fifo", like the IDT72142 would be pure gold, but it's obsolete, probably because everyone uses FPGAs nowadays. Does anyone know of a good way to clock serial data into a fifo, then pull it out in parallel (8 or 16 bit)? I was thinking about doing an FPGA, but I'd like to just drop in an IC and get this done.
Thanks !