Help with the Design of Non-linear Voltage divider biasing.

Discussion in 'Homework Help' started by micktosin, Mar 20, 2012.

  1. micktosin

    Thread Starter New Member

    Mar 20, 2012
    Hi there. I've been having trouble getting my head around how the Circuit shown below were designed, to get the values shown in the Circuit below.
    It's a frequency multiplier, which obviously means it is a non linear. So please can somebody help me with this, as i only know how to design a linear Voltage divider Bias Circuit.
    Please find the attached document below.
  2. hgmjr

    Retired Moderator

    Jan 28, 2005
    Can you provide the input point and the output point on this circuit? Is there more to the circuit than what you have pictured.

  3. micktosin

    Thread Starter New Member

    Mar 20, 2012
    Hi! The circuit below was retrieved from the circuit shown below. I Just need to know how the resistors values, of the stage shown in Red were calculated.
    Base on the spec provided with the transistor, I've been trying to work out how it was designed, especially R12 and R11.
    Any help will be a life saver. Thanks.
  4. hobbyist

    AAC Fanatic!

    Aug 10, 2008
    78L09 is a voltage regulator (google search),, so the bias resistors is still a linear calculation.
  5. panic mode

    Senior Member

    Oct 10, 2011
    in overtone circuit you get multiplication by tuning output circuit (L4 and C13) to a frequency that is multiple of input signal.

    when you introduce step to a under dampened circuit, you get osculations (decaying). but they do not decay fact enough (one trigger pulse will give you tens or hundreds of oscillation periods). but if you keep getting pulse say every three oscillations, your output will only decay a little before getting another boost.

    mechanical equivalent - swing. you do not need to push it EVERY period to sustain oscillation. providing push every second, or every third swing will work too. the key is that timing has to be right (exact multiple).
  6. micktosin

    Thread Starter New Member

    Mar 20, 2012
    I still don't know how to solve it, base on the explanation above. Please can you please explain how this transistor was bias into saturation? As i don't know how the Rc and Re were calaculated to have such a low resistance.
  7. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    Why are you stating the transistor is in saturation?

    As hobbyist suggests this is a relatively simple BJT biasing problem using a typical voltage divider bias topology.

    The 22k / 2.2k voltage divider with the 9V source will produce an open circuit [Thevenin] voltage of ~0.82V. The divider also has an effective source [Thevenin] resistance of 2kΩ.

    If we denote the voltage divider open circuit voltage output as Vth and the divider source resistance as Rth we may write the static base current as


    Where RE is the emitter resistance, VBE is the base emitter bias voltage and β is the DC current gain.

    We would also have the collector current as

    I_C=\beta I_B

    If the transistor has a DC β of say 90 and a VBE=0.65V then the base current would be IB=(0.82-0.65)/(2000+91*22)=42.5uA. This would give IC=3.83mA. I would make the point that the result is highly dependent on the actual VBE and β values. If VBE=0.7 V instead then IB=30uA and IC=2.7mA.

    The collector voltage would be close enough to 13.5V and the emitter voltage would be ~84mV with IC=3.83mA. So the transistor VCE would be close to 13.4 V which is well out of saturation. In fact it is getting "closer" to cut-off.

    I think the non-linear functionality will come from the base-emitter diode dynamic [ac] behavior.
    Last edited: Apr 25, 2012