Help with some code for a clock

Thread Starter


Joined Nov 13, 2011
I'm new to writing code. I'm currently working on code for a clock... a pretty standard homework application for students I know. I've been trying to teach myself verilog for sometime now, and I could some guidance.

Here's part of my code for the hour part of the clock. It takes clock input that's already down to the proper timing. I'm trying to get the code to count up to 12 then reset down to 0. The outputs A and B go to a 7 segment driver, and I'm using C to count to 12 and reset. But there's obviously something wrong or I wouldn't be asking. Thanks in advance.

module decimal_counter_20(A,B,CLK,RST);
input CLK, RST;

output [3:0] A;
output [3:0] B;

reg [3:0] A;
reg [3:0] B;
reg [4:0] C;

always @ (posedge CLK or negedge RST)

if (~RST)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;

else if (B < 9)begin
B = B + 4'b0001;
C = C + 5'b00001;

else if (B == 9)begin
A = A + 4'b0001;
B <= 4'b0000;

else if (C > 12)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;

A few comments:

- You have a few latches in this design. Your output signals should all be assigned in every single else/if. The easy way to do that is with default assignments.

- You're mixing non-blocking and blocking assignments in a clocked 'always' block. Though technically legal, this is most likely not what you wanted to do. In short, always use non-blocking assignments in clocked blocks and blocking assignments in combinatorial blocks.

- You need an else statement. You are most likely getting caught in an undefined state. You need to make sure that all conditions of your if/elses are fully covered. If you think about it, an if/else will get synthesized into a MUX.