I'm new to writing code. I'm currently working on code for a clock... a pretty standard homework application for students I know. I've been trying to teach myself verilog for sometime now, and I could some guidance.
Here's part of my code for the hour part of the clock. It takes clock input that's already down to the proper timing. I'm trying to get the code to count up to 12 then reset down to 0. The outputs A and B go to a 7 segment driver, and I'm using C to count to 12 and reset. But there's obviously something wrong or I wouldn't be asking. Thanks in advance.
-Drew
module decimal_counter_20(A,B,CLK,RST);
input CLK, RST;
output [3:0] A;
output [3:0] B;
reg [3:0] A;
reg [3:0] B;
reg [4:0] C;
always @ (posedge CLK or negedge RST)
if (~RST)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;
end
else if (B < 9)begin
B = B + 4'b0001;
C = C + 5'b00001;
end
else if (B == 9)begin
A = A + 4'b0001;
B <= 4'b0000;
end
else if (C > 12)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;
end
endmodule
Here's part of my code for the hour part of the clock. It takes clock input that's already down to the proper timing. I'm trying to get the code to count up to 12 then reset down to 0. The outputs A and B go to a 7 segment driver, and I'm using C to count to 12 and reset. But there's obviously something wrong or I wouldn't be asking. Thanks in advance.
-Drew
module decimal_counter_20(A,B,CLK,RST);
input CLK, RST;
output [3:0] A;
output [3:0] B;
reg [3:0] A;
reg [3:0] B;
reg [4:0] C;
always @ (posedge CLK or negedge RST)
if (~RST)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;
end
else if (B < 9)begin
B = B + 4'b0001;
C = C + 5'b00001;
end
else if (B == 9)begin
A = A + 4'b0001;
B <= 4'b0000;
end
else if (C > 12)begin
A <= 4'b0000;
B <= 4'b0000;
C <= 5'b00000;
end
endmodule