Help with Single-Stage Amplifier

Discussion in 'The Projects Forum' started by blah2222, Mar 30, 2011.

  1. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    Hello all,

    To give a little bit of background, I am working on this design project and the goal is to build a single-stage amplifier that performs linearly without clipping under a certain set of constraints. I am very familiar with small-signal analysis and have no problem solving problems, but this project has been keeping me busy for quite some time now, and I am hoping that someone can lend a hand.

    The amplifier is constrained by it's output swing, gain, output load, input resistance, power supply, and DC power dissipation.

    I really just want to know if my approach in designing this amplifier makes sense, rather than just getting someone to design it for me. That's partly why I don't want to post the values of the restrictions. But some important information about the restrictions is that the gain is very small, (less than 5), and phase isn't an issue, the output load is small, (less than 1k), the max output amplitude is less than 0.5 V, and the DC power dissipation is less than 0.5 W. Probably would have been easier to post my values, but again, I am not looking for someone to tell me how to build this, I just need to know if I'm on the right path. :)

    We are using an NPN 2N3904 BJT, and I have tried both the emitter bypassed and not bypassed with no luck on making a circuit that performs properly. For my current attempt at this, I am designing this amp with a bypassed emitter. Since we are given the gain, as well as the maximum output amplitude on the load, we are able to find the maximum input swing:

    |gain| = |vo|/|vin| = gm*RL (bypassed emitter)

    We are given the gain, and RL, so the small-signal transconductance is just:

    gm = |gain|/RL

    We also know that gm = vt*Ic = 40*Ic (room temperature)

    Therefore, Ic = gm/40, so now we have to work with that.

    Now this is the part where I get stuck. To continue on with the design, an assumption of beta (hfe, current gain) has to be made in order to calculate input terminal resistance (rpi) as well as the base current (Ib). When I read the datasheet: there seems to be so much variance in the current gain, for different Ic and Vce values. I know what my Ic is, based on calculations above, but is my next step to force my transistor to be biased for a certain Vce on the data sheet to maintain a good value for hfe? For instance, say my Ic was 10 mA, and looking at the typical current gain vs. Ic plot, it shows that hfe is roughly 225 at Vce = 5 V and Ic = 10 mA. Should I make sure that my transistor is DC biased so that Vce is 5 V, to ensure a consistent hfe?

    From there, the next problems lies in finding the four-resistor network values, which I am having trouble with calculating. For the base resistors that bias the base voltage between power and ground, should I assume that the current passing through them is significantly greater than Ib and just perform a voltage division to have the correct value placed on Vb to bias the transistor?

    I just don't know what approach to take when designing this, probably because I am not that experienced with all this stuff yet.

    Hopefully I didn't lose you guys, but I appreciate those who made it this far in the post and can actually help me out.

    Thanks a lot,
    Last edited: Mar 30, 2011
  2. blah2222

    Thread Starter Well-Known Member

    May 3, 2010
    Anyone have any thoughts? :)
  3. Adjuster

    Well-Known Member

    Dec 26, 2010
    If your collector load impedance was 500Ω, and you wanted a gain of only 5 times, this would imply a gm of about 10mS, and hence an Ic of around 250μA. The maximum output swing at the collector with the transistor being driven completely to clipping would then be about 250mVpk-pk. Serious distortion would result at much lower output levels.

    This may be adequate if an output swing quite a bit less than a couple of hundred mVpk-pk is acceptable. If not, you should consider leaving at least part of the emitter resistance un-bypassed, so that you can obtain the necessary low gain at a collector current which would permit higher output levels. You will also get less distortion because of the negative feedback added by this method. The resistance not to be bypassed is found by subtracting 0.025/Ic from RL/|gain|. NB here Ic is chosen to get sufficient output.

    If the voltage dropped in the unbypassed part of the emitter resistance by Ic is reasonable, say several hundred mV upwards, then this resistance may be sufficient for bias stability. If not, connect a second bypassed resistor in series to give a total around 10% of the supply voltage (ballpark figure). Add a typical Vbe to the emitter voltage get the base voltage.

    Your base potential divider could be designed to run with a total current of 10 times the typical base current, but if the spread is very big you might want to increase this to 10 times the base current at minimum HFE.
  4. wayneh


    Sep 9, 2010
    Depending on the transistor and the situation, base current can become significant, so that it's not always practical to plan on having 10x or more current just for bias. Unless you waste a bunch of current through the bias resistors, the base current may well become a significant factor in calculating Vb.
  5. Adjuster

    Well-Known Member

    Dec 26, 2010
    If a bias chain current ten of ten times the expected base current looks like being too much, consider using a current of N*Ib for the resistor returned to common, (N+1)*Ib for the resistor returned to Vcc. Choose the value of N according to how much bias voltage variation is acceptable, bearing in mind the compromise with current consumption.

    You might also need to consider the effect of bias chain resistors on the input impedance. This may be more significant if there is an un-bypassed emitter resistor, as the input impedance at the base may then be less than the bias resistance.

    Example: at 1mA collector current in a small silicon transistor with a 560Ω emitter resistor RE, the base voltage might be roughly 1.2V. The bias resistor at the common end of the chain for IR=10*Ib would then be 1.2V/(10*1mA/100) = 12kΩ. The upper resistor would depend on Vcc.

    If the current gain was 100 and the collector current was 1mA, the common-emitter input impedance with RE bypassed with a large capacitor might be about 2.6kΩ. If RE was not bypassed, the input impedance would be increased to about 59kΩ.