Help with reading schematic

Thread Starter

Manish Chowdhary

Joined Jul 29, 2017
4
upload_2017-7-29_16-45-8.png

Hi,
I am very novice person here, I need some help to read this schematics .
In the above figure I see that ICS872S06 , has CLK_EN ( pin 51 ) input this needs to be driven low in order to enable the chip.
PLD6_OUT_PROC_CRC_CLK_EN_N can be driven via a GPIO that I need to code.
What I am not understanding from schematic is the role of +3.3VCS which connects to this signal.
Can someone help?
 

WBahn

Joined Mar 31, 2012
25,090
The signal is NOT connected to +3.3VCS. There is a 3.3 kΩ resistor between the two.

The resistor pulls the signal up when no signal is driving that pin so that, by default, the clock is disabled. Hence, it is called a "pullup" resistor.
 

Thread Starter

Manish Chowdhary

Joined Jul 29, 2017
4
upload_2017-7-30_21-43-15.png
Followup query on the schematic I am working with, basically I am working on a circuit that generates clock signals using PLL and CRC chips.
I have to initialize this circuit and one of the steps specified to initialize the circuit is to driver ENABLE_1P2V_DELAY_N as low via GPIO operation, I am not sure what exactly is this doing, can someone help with reference to the part of schematic that has been posted?
 

#12

Joined Nov 30, 2010
18,173
am not sure what exactly is this doing, can someone help with reference to the part of schematic that has been posted?
The parts you circled are n-channel, enhancement style mosfets. They function as inverters and resemble an NPN transistor in their function, but mosfets require much less controlling current on their gates and act as much better conductors from drain to source terminals when turned on by a positive signal to their gates. When their gates are high, their drains become low.
 
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