Hi,
I am very novice person here, I need some help to read this schematics .
In the above figure I see that ICSXXXXXX , has CLK_EN ( pin 51 ) input this needs to be driven low in order to enable the chip.
PLD6_OUT_PROC_CRC_CLK_EN_N can be driven via a GPIO that I need to code.
What I am not understanding from schematic is the role of +3.3VCS which connects to this signal.
Can someone help?

 

The signal is NOT connected to +3.3VCS. There is a 3.3 kΩ resistor between the two.

The resistor pulls the signal up when no signal is driving that pin so that, by default, the clock is disabled. Hence, it is called a "pullup" resistor.

 

Welcome to AAC!
That GPIO pin is pulled up to 3.3V via a 3.3k resistor so that, by default, the clocking of the IC is disabled.

Edit: WBahn beat me to it!

 

This MOSFET will do the job
https://www.infineon.com/cms/en/pro...?productType=5546d462533600a401533d4a7a127014

 

This MOSFET will do the job
https://www.infineon.com/cms/en/pro...?productType=5546d462533600a401533d4a7a127014

Jony130 thanks for the response however I am looking for more basic answers that would help me to learn about this circuit.
Thanks in advance!

 

am not sure what exactly is this doing, can someone help with reference to the part of schematic that has been posted?

The parts you circled are n-channel, enhancement style mosfets. They function as inverters and resemble an NPN transistor in their function, but mosfets require much less controlling current on their gates and act as much better conductors from drain to source terminals when turned on by a positive signal to their gates. When their gates are high, their drains become low.

 

The trailing # may be a convention for NOT.

The circles at the input, sort of, confirm that