Hi, I have a 1Hz pulse and wish to obtain a very short pulse at the low edge of the 1Hz pulse. The following is what I'm referring to:



Since I cannot use a capacitor, I was thinking maybe something with flip flops but I'm still a bit stuck.

Thank you

 

Perhaps you could define "very short"? Is that pulse in the range of a one shot?

 

What you want to explore is called an 'edge trigger'. There are both negative going(what your showing) and 'positive going'. A link to doing it with a flip-flop; http://eelab.usyd.edu.au/digital_tutorial/part2/flip-flop02.html

 

It ain't pretty and may need some serious tweaking. I did this many years back, I don't remember did I actually use a gate or did I build this up with transistors and a diode AND function but here goes.

Two inverters in series will have a brief moment when the input rises where both outputs are low; also a brief moment when the input falls where both are high. If you can catch that event you have an edge detector.

Well you said no caps!

 

If you intervene a capacitor between pin 4/9 and Ground maybe you could prolong the charging delay of the second NOR gate.
I haven't tested it, talking completely based on taught stuff.

I know you said no caps, but maybe you weren't referring to such an application. Alternatively, since the theory is to increase the load of the second NOR gate, you could just try to drive more IC inputs with it, just to increase the load it "sees", without any other logical effect.

 

It ain't pretty and may need some serious tweaking. I did this many years back, I don't remember did I actually use a gate or did I build this up with transistors and a diode AND function but here goes.

Two inverters in series will have a brief moment when the input rises where both outputs are low; also a brief moment when the input falls where both are high. If you can catch that event you have an edge detector.

Well you said no caps!

If the resulting pulse is too short, any odd number of gates (inverters) in series will produce the same result, with the resulting output pulse width being equal to the propagation delay of one inverter, multiplied by the number of inverters in series.