I need to build a circuit that will produce the behavior shown in the attached image.

S - Machine Signal - On during run cycle and Off at cycle end

R - Reset

Q - End of Cycle Alarm

I need the alarm to activate when the machine cycle ends and remain on until the operator presses the Reset button. The alarm should not reactivate when the Reset button is released. The alarm should remain off until the end of the next machine cycle, regardless of how many times it is pressed.

I am a digital electronics virgin, but after some reading today, I believe something like a J-K latch or an edge activated latch could be appropriate?

All inputs greatly appreciated!

Regards,

Donovan

 

Use a D Flip Flop with a reset input (such as the 7474). Feed a 1 to its input. Its output will be your alarm signal.
The machine signal will trigger the FFs clock through a NOT gate. That way, when it goes from HIGH to LOW the FF will output a 1 until it is reset by the reset button.


Pretty basic, is that clear?

 

I think I understand.

Assuming this 7474 chip is appropriate, you are saying I can achieve the desired behavior by connecting a high signal to pin "SD", machine signal to pin "CP", and the alarm to pin "Q", correct? On a chip like this, are the inputs with the lines over them the NOT versions... sort of like getting an inverted copy, or is the other half of the IC just a copy of the other circuit?

Can you recommend a good set of articles that shows the associated truth table and describes functionality form the ground up?

Thanks for your quick response!

Regards,

Donovan

 

Just as you said \(Q\) and \(\bar{Q}\) are the outputs of the IC, complementary to each other. \(\bar{Q}=NOT(Q)\)

The IC you suggested is a match.

There isn't a truth table worthy of mention, the operation is pretty basic. Check the wikipedia article if you want: http://en.wikipedia.org/wiki/D_flip_flop#D_flip-flop