Hey everyone! I'm really confused on how to make a countdown timer in VHDL. A timer that counts up I can do, but a countdown one that takes input from switches on the board confuses the living being out of me.
The ports are as follows: entity timer is
port( clock: in std_logic;
start: in std_logic;
InitialTime: in std_logic_vector (5 downto 0);
seg: out std_logic_vector(0 to 6);
dp: out std_logic;
an: out std_logic_vector(0 to 3);
done: out std_logic
);
I'm having trouble figuring out how I'll be able to make it countdown from 00 to 59 again and have the minutes decrement as well. Done outputs a "1" when countdown has reached 00:00. InitialTime is set with 6 switches on the board, so I'm also wondering how I'll be setting up the time with the 6 switches.
This whole thing is giving me a giant headache, so having ANY kind of helpful insight on how to design this circuit will be GREATLY appreciated!
Please help!
The ports are as follows: entity timer is
port( clock: in std_logic;
start: in std_logic;
InitialTime: in std_logic_vector (5 downto 0);
seg: out std_logic_vector(0 to 6);
dp: out std_logic;
an: out std_logic_vector(0 to 3);
done: out std_logic
);
I'm having trouble figuring out how I'll be able to make it countdown from 00 to 59 again and have the minutes decrement as well. Done outputs a "1" when countdown has reached 00:00. InitialTime is set with 6 switches on the board, so I'm also wondering how I'll be setting up the time with the 6 switches.
This whole thing is giving me a giant headache, so having ANY kind of helpful insight on how to design this circuit will be GREATLY appreciated!
Please help!