hello everyone,

I took the Digital Electronics course this semester, and my teacher gave me the project in VHDL :

8-bit CLA adder
8-bit CLA adder with 2 x 4-bit CLA adders
16-bit CLA adder
16-bit CLA adder rith 2 x 8-bit CLA adders

Since Im new to this area, IM TOTALLY CONFUSED ABOUT GENERATE - PROPAGATE etc..... However, i managed to write the vhdl code for the 8-bit CLA adder and the 16-bit CLA adder. My problem is with the other two circuits "8-bit CLA adder with 2 x 4-bit CLA adders" and "16-bit CLA adder rith 2 x 8-bit CLA adders".

PLEASE if anyone can help me by sending the vhdl codes for these circuits, it would help me a LOT......

thank you all
fasmatikos

 

I have not looked at the intimate details of a carry lookahead adder. What I do know about binary arithmetic is based on the possible combinations of generate, propagate, operand A, and operand B.

The idea behind generate and propagate is to derive a set of combinatorial eqautions so that the generation of the carries and the result does not depend on the generation of the result from the previous stage. It basically computes everything at once all in parallel, with a fixed delay that is less than the delay in a ripple carry adder.

It frightens me, a bit, to think of chip designers writing VHDL without understanding what is going on under the hood. Promise me you'll dig in and understand this stuff before moving on. Pay particular attention to the resource counts that the synthesizer will give you as an output. This will explain why doing a 16 bit adder is different than cascading two 8-bit adders. Maybe the synthesizer is smart enough to figure out what you are doing and maybe it's not.