Hello
Once again I am here begging for advice. I have included two rudimentary diagrams for the logic portion of my circuit.
*Please excuse the figures, I could not find quad components in LTSpice and looked online for downloads but did not find any so I simply placed the components of one device together (i.e. A1 and A2 are part of one quad clocked d latch and A5 and A6 are part of the other) and I used the Pre input to signify the Polarity.*
In fig 1 it is seen that I am using two LM14042B quad clocked d latches (I only use two channels from each one) to send signals out. They are wired so that the upper one clocks at Vss and the lower one clocks at Vdd. This setup works correctly by storing data from the previous output of the upper into the lower one so that this data can be sent to change the functioning of the upper one when the clock signal goes low. Anyway, it is a fairly simple setup that produces a repeating sequence out of the upper one like this:
Q1 Q1bar Q2 Q2bar
0 1 0 1
1 0 0 1
1 0 1 0
0 1 1 0
These signals do work to control the logic MOSFET's I am using for the power output. However, it is energizing two circuits at once and I would like to change the final output to one output at a time by using a quad AND gate (I am trying to use an NTE74LS08) in the configuration seen in fig 2 so that the final output would be:
Q1 Q1bar Q2 Q2bar
0 0 0 1
1 0 0 0
0 0 1 0
0 1 0 0
Again, the logic is simple and works well on paper but when I attach to the AND gate things stop working. I am using an NE555N timer which does its job well and has a 220 uF and 0.1 uF capacitor across the inputs as previously recommended to keep from causing signal corruption. I have tried using various resistors and diodes from different outputs but no significant effect was seen. In other words, I don't know what I am doing here so any advice on how to make this AND gate function is greatly appreciated.
Once again I am here begging for advice. I have included two rudimentary diagrams for the logic portion of my circuit.
*Please excuse the figures, I could not find quad components in LTSpice and looked online for downloads but did not find any so I simply placed the components of one device together (i.e. A1 and A2 are part of one quad clocked d latch and A5 and A6 are part of the other) and I used the Pre input to signify the Polarity.*
In fig 1 it is seen that I am using two LM14042B quad clocked d latches (I only use two channels from each one) to send signals out. They are wired so that the upper one clocks at Vss and the lower one clocks at Vdd. This setup works correctly by storing data from the previous output of the upper into the lower one so that this data can be sent to change the functioning of the upper one when the clock signal goes low. Anyway, it is a fairly simple setup that produces a repeating sequence out of the upper one like this:
Q1 Q1bar Q2 Q2bar
0 1 0 1
1 0 0 1
1 0 1 0
0 1 1 0
These signals do work to control the logic MOSFET's I am using for the power output. However, it is energizing two circuits at once and I would like to change the final output to one output at a time by using a quad AND gate (I am trying to use an NTE74LS08) in the configuration seen in fig 2 so that the final output would be:
Q1 Q1bar Q2 Q2bar
0 0 0 1
1 0 0 0
0 0 1 0
0 1 0 0
Again, the logic is simple and works well on paper but when I attach to the AND gate things stop working. I am using an NE555N timer which does its job well and has a 220 uF and 0.1 uF capacitor across the inputs as previously recommended to keep from causing signal corruption. I have tried using various resistors and diodes from different outputs but no significant effect was seen. In other words, I don't know what I am doing here so any advice on how to make this AND gate function is greatly appreciated.
Attachments
-
29.8 KB Views: 31
-
24.7 KB Views: 24