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recently i'm working on asking a ai to generate a power supply for zynq 7000 series
the topology is 4 dcdc ＋ADM1186
the question is:
The AI was instructed to sequence a power tree. Instead of using a traditional voltage divider to monitor the actual analog rail, the AI did this:
1. It took the open-drain PGOOD signal from an upstream DC-DC converter.
2. It added a pull-up resistor to 3.3V.
3. It fed this PGOOD directly into the VIN1 pin of the ADM1186.
According to the ADM1186 datasheet, the VINx pins are comparators with a strict 0.6V threshold. AI calculated that a 3.3V pulled-up signal is strictly greater than 0.6V. So, when PGOOD goes high, it triggers the sequencer. Electrically, it bypasses the need for a voltage divider，Is this plan feasible
the topology is 4 dcdc ＋ADM1186
the question is:
The AI was instructed to sequence a power tree. Instead of using a traditional voltage divider to monitor the actual analog rail, the AI did this:
1. It took the open-drain PGOOD signal from an upstream DC-DC converter.
2. It added a pull-up resistor to 3.3V.
3. It fed this PGOOD directly into the VIN1 pin of the ADM1186.
According to the ADM1186 datasheet, the VINx pins are comparators with a strict 0.6V threshold. AI calculated that a 3.3V pulled-up signal is strictly greater than 0.6V. So, when PGOOD goes high, it triggers the sequencer. Electrically, it bypasses the need for a voltage divider，Is this plan feasible
