# Help with a semi persistent logic gate problem

Discussion in 'The Projects Forum' started by sniper98g, Aug 29, 2012.

1. ### sniper98g Thread Starter New Member

Aug 29, 2012
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I have a project that I'm sure I can make a circuit for if I can just get my head wrapped around the logic. Unfortunately it has been over a decade since the last class I took in logic gates and I seam to have forgotten most of it.

I need a gate system that will remain at a 0 output until it receives a 1 on both of two inputs. It will then remain at a 1 output as long as either of the two inputs still have a 1 input and then when both inputs are back to a 0 the output will drop back to 0.

Any help with this would greatly appreciated.

2. ### Papabravo Expert

Feb 24, 2006
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I don't think this is a combinatorial gate problem. It sounds like you need some memory to do the sequencing.

3. ### absf AAC Fanatic!

Dec 29, 2010
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Is this what you're looking for?

Allen

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4. ### Papabravo Expert

Feb 24, 2006
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That certainly is a non-combinatorial solution. You might want to mention that in this configuration the D and the Clock input should be tied high. It would not do for them to be beating up and down at high frequency, which they will if they are left open.

absf likes this.
5. ### kubeek Expert

Sep 20, 2005
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You need an S-R latch, two ANDs, one OR and one NOR. Sadly I dont have a suitable logic symbol for the latch, so I have to explain it in words.

Inputs A,B go in a pair to one AND, to NOR and to OR gate.
Output of AND goes to S input, output of NOR goes to R input of the latch.
Output of the latch and output of the OR both go to the remaining AND where you take your output.

Could anybody put that in a picture?

Last edited: Aug 30, 2012
6. ### absf AAC Fanatic!

Dec 29, 2010
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Is your S-R latch active high 4013 or active low 7474?

Allen

7. ### crutschow Expert

Mar 14, 2008
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You only need two chips for absf's solution. I think that's about as simple as you can get, other than using a micro.

8. ### kubeek Expert

Sep 20, 2005
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I was thinking in positive logic, but your solution is much more elegant.

absf likes this.