help to Optimize my Cadsoft Eagle work

Thread Starter

vinodquilon

Joined Dec 24, 2009
234
Here I am presenting my first serious practical work in Cadsoft Eagle
with a very simple circuit.
See the attachment.
Help to optimize my work by pointing any faults (if have) in my work.

I Used the schematic as reference to place components.
I used wire width 0.024
Is it enough for etching ?

Four wires are drawn on component side. But this is one sided board.
So I will connect four direct wires (without soldering) on component side between desired points.
After auto route (Preferred directions 1 Top-N/A, 16 Bottom-*) these four
wires remain unrouted. Its manual routing on solder side is so tedious as of crossings.
So I manually route them through component side. That is wire jumps.
Does it is a good practice ?

Does there any need for turning on/off any additional layers on component and solder side ?

I heartily welcoming all opinions to improve my skill in Eagle PCB fabrication.
 

Attachments

jpanhalt

Joined Jan 18, 2008
11,087
1) You don't seem to have the power pins connected on the schematic. Did it pass ERC? The manual/help menu tells you how to find and place them for IC's using the the Invoke button. You can also just try the Invoke button without going to help. It is the button with 4 IC gates on the lower right of the menu. It is pretty intuitive to use.

2) Posting a pdf is nice for just seeing what you have done, but there is a lot missing from the board pdf. AAC will allow you to post .sch and .brd Eagle files. If you will post those files, we might be able to give you much better help.

3) BTW, I use autoroute just to see how things fit. I then manually route everything. I treat that exercise as a puzzle and challenge to solve.

4) 0.024 is OK for track widths and will etch well. If the board space allows it, 0.032 may work with fewer problems for your very first attempt.

John
 

Thread Starter

vinodquilon

Joined Dec 24, 2009
234
1) You don't seem to have the power pins connected on the schematic. Did it pass ERC? The manual/help menu tells you how to find and place them for IC's using the the Invoke button. You can also just try the Invoke button without going to help. It is the button with 4 IC gates on the lower right of the menu. It is pretty intuitive to use.



Hi John,
Your comments are very useful.
Even without invoking power pins of ICs on schematic diagram, you can see
that on solder side the IC power pins are already connected to JP2.
Then what is the need for separate invoking ?
 

Thread Starter

vinodquilon

Joined Dec 24, 2009
234
1)
2) Posting a pdf is nice for just seeing what you have done, but there is a lot missing from the board pdf. AAC will allow you to post .sch and .brd Eagle files. If you will post those files, we might be able to give you much better help.


John
Hi John,

Here I am attaching the desired files. Hoping for more improvements
in my final board.
 

Attachments

jpanhalt

Joined Jan 18, 2008
11,087
True, I went back and reviewed the pdf's and noticed what you had done. At a minimum, it is much easier to read a brd file when it is in color and both sides show on the same image.

I still recommend posting the sch and brd files and believe that will get you the best advice.

OOPS, cross posted. Ignore this post.

John
 

SgtWookie

Joined Jul 17, 2007
22,230
Vino,
When you are routing between the pins of DIP packages, 0.024" is about the practical limit. If you go any larger than that, you may have problems with incomplete etching and/or solder bridges.

If you use the Polygon tool to create a "copper pour" over the board, it will help you to save etchant. There really is no good reason to etch away all of the copper that is not a trace. If you give the Polygon a name like "GND" or "VDD", it will automatically connect together all of the matching signal names without having to route them - if there is a path.

The Polygon tool takes just a little bit of getting used to, but once you master it, you will find it very powerful and useful.

Please note that you should never have Width set to less than 0.010" when placing a Polygon. I suggest setting Isolate and Spacing to 0.016" or 0.024". If you allow orphans, then otherwise unreachable areas will also have a copper fill.
If Thermals are on, it will make soldering to pads easier, but the traces connecting to pads will be much more narrow. I usually have Thermals turned off.

Note that the Autorouter runs traces right through pads. This is OK if the board will be made by a PCB house, as the pads/vias will be through-plated and therefore stronger, but it can cause problems if you are going to make the boards yourself, as it is all to easy to "lift" a pad off the board due to getting it too hot during soldering. It is a good idea for homemade boards to have only ONE trace connecting to a pad or via. If you accidentally lift a pad, it will be much easier to effect a repair.

Here is an example of what I'm talking about:



Note that some of the pads (particularly the circular ones) are very thin. You can use the DRC "restring" function to increase the size of the pads. For example, start DRC in the board, and click the Restring tab. Look in the top three % figures; they are all 25. Try changing them all to 35, and click Apply. You will notice that all of the pads increase in size.

When you do that, be careful that you do not make the pads overlap the traces that are already routed. Completing the DRC will make sure that there is enough clearance.
 

Attachments

SgtWookie

Joined Jul 17, 2007
22,230
Vino,
I neglected to mention that your base resistors R1-R4 are too high in value. Reduce them to be in the range of 1k to 1.2k Ohms (very rough estimation.)

If you want a better estimation of the base resistors to saturate the transistors, then calculate:
Rbase = (Vout-Vbe)/(Ic/10)
where:
Vout is the output voltage of the flip-flops when high. LS TTL is typically 3.4v, but it can be as low as 2v under load.
Vbe is the base-emitter voltage of your transistor. You can use 0.7v as a rough estimate.
Ic is the current required through your load; the LEDs.
If you assume that the TTL out will be 3v, Vbe is 0.7v, and you want 20mA through the LEDs, then:
Rbase = (3-0.7)/(20mA/10) = 2.3/0.002 = 1,150 Ohms. Your mileage may vary.

Also, you do not have current limiting resistors for the LEDs. Unless you include them, you risk rapidly burning them out. Each LED should have it's own current limiting resistor.
Rlimit >= (Vcc-Vf_LED)/DesiredCurrent

Do not depend upon the hFE of the transistor to limit the current through the LEDs, as the hFE will vary quite a bit depending on temperature.
 
Last edited:

Thread Starter

vinodquilon

Joined Dec 24, 2009
234
Vino,
I neglected to mention that your base resistors R1-R4 are too high in value. Reduce them to be in the range of 1k to 1.2k Ohms (very rough estimation.)

If you want a better estimation of the base resistors to saturate the transistors, then calculate:
Rbase = (Vout-Vbe)/(Ic/10)
where:
Vout is the output voltage of the flip-flops when high. LS TTL is typically 3.4v, but it can be as low as 2v under load.
Vbe is the base-emitter voltage of your transistor. You can use 0.7v as a rough estimate.
Ic is the current required through your load; the LEDs.
If you assume that the TTL out will be 3v, Vbe is 0.7v, and you want 20mA through the LEDs, then:
Rbase = (3-0.7)/(20mA/10) = 2.3/0.002 = 1,150 Ohms. Your mileage may vary.

Also, you do not have current limiting resistors for the LEDs. Unless you include them, you risk rapidly burning them out. Each LED should have it's own current limiting resistor.
Rlimit >= (Vcc-Vf_LED)/DesiredCurrent

Do not depend upon the hFE of the transistor to limit the current through the LEDs, as the hFE will vary quite a bit depending on temperature.
I think 1K would be suit well.
 
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