Hello,

I am trying to test a D flip flop using the following circuit. i am using HD74LC74 dual d-flip flop ic. I have attached the data sheet below. I am using a 6 volts, 4.5 amp battery. the schematics is as shown below.

initially i keep both the switch s1 and s2 open. and i switch the power on. The out put of q shows high. Why is this happening. how can i prevent the flip flop Q out put giving a logical high on when i switch the power on?

 

Be careful - you are operating the logic right at the maximum voltage before the smoke comes out. The IC will be much happier running at 5 volts.

You may notice the 7474 has a SET and a RESET line. It is conventional to either use a switch to RESET the flip flop, of an RC circuit and a Schmitt trigger input gate to hold the RESET level for a brief period after power on to leave the logic in a known state.

Some sort of arrangement for a power on reset signal is quite conventional for logic systems so they come up in a known state.

 

For power on reset, connect 100nF to ground, and 10K to Vcc, to the reset pin.
You will still probably have problems with contact bounce on the clock switch. Google "debounce circuits".