Right you are, my error. So then it becomes,I 'm quite positive that the transmission gate doesn't invert the signal it transmits.
http://en.wikipedia.org/wiki/Transmission_gate
Its control pin might be complementary, but that depends on the way you hook it up.
I mentioned that too on my first post, but I think the teacher wanted to find a simple example to work on transistor level, without adding too much complexity by adding a whole D-FF in the circuit.Looking at the first inverter input, the inverters input will be whatever is at Vin when
Phi1 = 1. However, when Phi1 = 0, there is no logic level since the CMOS switch (transmission gate) will be off.
x=Don't care. The value of Vi can be anything and it will not cause an change of state.What is x?
It was mentioned this is a dynamic shift register. I think a design like this 'might' work reliably above some minimum frequency if there was sufficient gate capcitance. Dynamic RAM uses very simple cells which rely on tiny capacitances to retain state until refreshed.Looking at the first inverter input, the inverters input will be whatever is at Vin when
Phi1 = 1. However, when Phi1 = 0, there is no logic level since the CMOS switch (transmission gate) will be off. In a real
transistor there will be parasitic capacitance that maintains charge and keeps the logic level at what it
was when the CMOS switch was on.