Does anyone have any tutorial about cmos tg dynamic shift register? I need an explaination how this circuit works.
Hmph.... good question. It may need both edges (positive going and negative going) to complete a cycle. With overlapping clocks, it wont get both. I may be completely wrong, but hopefully someone proving me wrong will help you more
As you see this register is consist of two dynamic d lip flop. I need to prove why this circuit can't work with overlapping clocks.
I really need help because I know that when we use overlapping clocks all transmission gates are on at the same time.
Are those "pump" thingies inbetween the inverters transmission gates? If so and I get the notion of overlapping clocks correctly, here is a thought: If high pulses from both clocks coincide in the same time moment, then both φ1 and φ2 gates will allow a signal to pass through. In that case v1 will have an uninhibited path through 4 NOT gates towards the output of the circuit, banishing the essense of the shift register. For the circuit to work correctly, HIGH pulses from both clocks must never overlap. P.S. By the way, I think the output of a disabled transmission gate is high-Z, and I don't know if this would work for our circuit. A latch would make more sense. Maybe this symbol already stands for a latch and I have proven that "I age whilst always learning".
This shift register have 4 cmos transmission gates and 4 cmos inverters. I know if Phi1 and Phi2 are high at the same time(clcok overlap) all transmission gates are on at the same time,and data can pass through all stages at the same time.
Try induction (sorta): If clk(i) is HIGH, then TG(i) conducts and the result from NOT(i-1) is fed to the Gates of NOT(i). Thus signal(i-1)=NOT signal(i). So if in a continuous branch you have clk(i)=HIGH in a given moment, i=k...j, then you have signal(j)=NOT signal(k) if j-k is odd or signal(j)=signal(k) if j-k is even. This result is not acceptable, as it would be expected after j-k clock cycles, by definition of the Shift Register. Or you could outdo yourself and simulate the whole thing, blowing any suspicions away.
Are you confusing clock overlap with synchronous counting? Or am I? You say they are high at the same time.. This is a definition of synchronous counters Can you show an image of what the clock LOOKS like? In order to overlap a clock, you would need 2 clocks. hence OVER LAP. http://www.allaboutcircuits.com/vol_4/chpt_11/3.html Does this link make sense to you?
If θ1 and θ2 are high at the same time, then Vo8=Vi and the final sate of Vo8 will be determined by the sate of Vi when either θ1 or θ2 goes low (It does not matter which). The value if Vi would be passed all the way throiugh, not shifted through. Edit: {Further explanation of this. Since the tranmission gate inverts and the inverters also invert when enabled, if both θ1 and θ2 are high, then: --> Vo1 = -(Vi), (i'm using -(x) to denote NOT x) and Vo2 = -(V01) --> Vo2 = Vi and Vo3 = -(Vo2) --> Vo3 = -(Vi) and Vo4 = -(Vo3) --> Vo4 = Vi and Vo5 = -(Vo4) --> Vo5 = -(vi) and Vo6 = -(Vo5) --> Vo6 = vi and Vo7 = -(Vo6) --> Vo7 = -(vi) and Vo8 = -(Vo7) --> Vo8 = vi There is certainly are more elegant way to express this, but you have to do something, right?} However, if θ1 and θ2 do not over lap then; Given the SR starts from a reset (t0) condition (Vo2=L; Vo4=L; Vo6=L; Vo8=L) and following the state table below: -------Condition------:----------Result--------------- t1a, θ1=H, θ2=L, Vi=H --> Vo2=H; Vo4=L; Vo6=L; Vo8=L t1b, θ1=L, θ2=H, Vi=x --> Vo2=H; Vo4=H; Vo6=L; Vo8=L t2a, θ1=H, θ2=L, Vi=L --> Vo2=L; Vo4=H; Vo6=H; Vo8=L t2b, θ1=L, θ2=H, Vi=x --> Vo2=L; Vo4=L; Vo6=H; Vo8=H t3a, θ1=H, θ2=L, Vi=L --> Vo2=L; Vo4=L; Vo6=L; Vo8=H t3b, θ1=L, θ2=H, Vi=x --> Vo2=L; Vo4=L; Vo6=L; Vo8=L So, the only way for the shift register to work is for θ1 and θ2 to not overlap.
I 'm quite positive that the transmission gate doesn't invert the signal it transmits. http://en.wikipedia.org/wiki/Transmission_gate Its control pin might be complementary, but that depends on the way you hook it up.
Right you are, my error. So then it becomes, Vo1 = Vi and Vo2 = -(V01) --> Vo2 = -(Vi), (i'm using -(x) to denote NOT x) and Vo3 = Vo2 --> Vo3 = -(Vi) and Vo4 = -(Vo3) --> Vo4 = Vi and Vo5 = Vo4 --> Vo5 = Vi and Vo6 = -(Vo5) --> Vo6 = -(Vi) and Vo7 = Vo6 --> Vo7 = -(Vi) and Vo8 = -(Vo7) --> Vo8 = Vi Which has the same net effect in the end.
-------Condition------:----------Result--------------- t1a, θ1=H, θ2=L, Vi=H --> Vo2=H; Vo4=L; Vo6=L; Vo8=L t1b, θ1=L, θ2=H, Vi=x --> Vo2=H; Vo4=H; Vo6=L; Vo8=L t2a, θ1=H, θ2=L, Vi=L --> Vo2=L; Vo4=H; Vo6=H; Vo8=L t2b, θ1=L, θ2=H, Vi=x --> Vo2=L; Vo4=L; Vo6=H; Vo8=H t3a, θ1=H, θ2=L, Vi=L --> Vo2=L; Vo4=L; Vo6=L; Vo8=H t3b, θ1=L, θ2=H, Vi=x --> Vo2=L; Vo4=L; Vo6=L; Vo8=L When Vin=H Vo2=L. What is x?
I mentioned that too on my first post, but I think the teacher wanted to find a simple example to work on transistor level, without adding too much complexity by adding a whole D-FF in the circuit. It's a pretty lame excuse though, as in the end, the exercise theaches you about a cicuit that doesn't work in real life.
I can add two more d flip flops, so the circuit can work as 4-bit dynamic shift register, you ment on that?
It was mentioned this is a dynamic shift register. I think a design like this 'might' work reliably above some minimum frequency if there was sufficient gate capcitance. Dynamic RAM uses very simple cells which rely on tiny capacitances to retain state until refreshed.
As far as this exercise is concerned, I think the proposals on posts #7 an #12 cover it. Ohter than that, you don't need to linger too much on such a theoretical circuit, in my opinion.