# Help me understand synchronous counter with parallel load ?????

Discussion in 'Homework Help' started by corabict, Dec 29, 2012.

1. ### corabict Thread Starter New Member

Dec 29, 2012
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hey guys
i really need to understand this topic Counter with parallel load
i've a text book in my faculty & that diagram is in it

so can any one explain it to me, please ?

Last edited: Dec 29, 2012
2. ### WBahn Moderator

Mar 31, 2012
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Explain what you can about it based on the diagram. Imagine that you simply had to explain it to a student that was a year behind you. Do the best you can and we will help you correct and improve your explanation.

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3. ### corabict Thread Starter New Member

Dec 29, 2012
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ok
At first we have twoo main states
1- to Enable the
Code ( (Unknown Language)):
1. count
the load must be at logic 0
2- & we can enable the load regardless of the value of the count

because this is a synchronous counter then we will assume that Clk is at logic high (1) all the time

so let's assume that we wanna load the data which is 0010

Thx I've figured it out .....

my fault but i will be greedy a little ... so
1-is there is a better design for such circuit
2-what should i do to acquire the skill of designing circuits like this rather than just studying them ?????

i'm really very grateful to u WBahn ..

4. ### Papabravo Expert

Feb 24, 2006
11,210
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In order to answer the first question you need to define what "better" means. This circuit has been known for 50 years or more and the definition of "better" has changed at least three times over that period.

The answer to the second question is "if you can get the requirements clear" you can crank out a design that "meets the requirement". From there you apply the process of stepwise refinement until it is a good as it needs to me

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5. ### corabict Thread Starter New Member

Dec 29, 2012
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oh what i meant by better is a circuit that fulfill the same requirements & yet using less components & gates .. that would mean faster & more efficient

6. ### MrChips Moderator

Oct 2, 2009
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4,356
Most 4-bit binary counters come with LOAD, eg.
TTL 74177, 74161, 74163
CMOS 4029, 40193, 4516.

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7. ### corabict Thread Starter New Member

Dec 29, 2012
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a lot of thanks to all of u ....

8. ### Papabravo Expert

Feb 24, 2006
11,210
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The "minimum number of gates" was the standard of better from about 1952 to about 1970. Once integrated circuits were fabricated, it changed to the "minimum number of packages" on a board. Nowadays you can cram so much logic into an FPGA it is not worth the "expensive engineers" time to look for improvements at the gate level. You write a verilog or VHDL script and the software does the optimization. That is why I said the definition of "better" has changed at least three times since the first computer was built.

9. ### WBahn Moderator

Mar 31, 2012
20,416
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This is faulty reasoning. It is synchronous because the state outputs change in response to the same clock signal. Also, if Clk is high all the time, then the outputs will never change at all (unless you take the Clear LO, since it is an asynchronous input -- probably). These JK Flip Flops (JKFFs) are positive-edge triggered, meaning that the J and K inputs are sampled and the output value updated in response to a rising edge (LO-to-HI transition) on the Clk input.

Also, your diagram doesn't specify an input level for Clear. This input HAS to be held HI in order to load a value (or count).

That is a really loaded question (and one of my pet peeves with most textbooks and many instructors). Rest assured, none of what I am about to say is directed at you -- it is a perfectly reasonable question for a student to ask. My problem is when text books or instructors just tell students to "simplify" something or to make it "better" or to "optimize" something without specifying by what metric "simple", "better", or "optimal" are to be measured -- and, yes, I am still guilty of it occasionally myself, but I think I have gotten pretty good at catching myself.

For instance, consider the following Karnaugh map for the output Y:

 AB 0 1 0 1 1 1 1 0

Many people would look at this, group the two pairs of 1's in the table, and produce the following "simplest" or "optimal" expression.

Y = A' + B'

If implemented directly in normal CMOS, this would require ten transistors and exhibit three gate delays from input to output. Yet this Karnaugh map is nothing more than the truth table for a 2-input NAND gate and

Y = (AB)'

only requires four transistors and a single gate delay.

So if given an expression and asked to "simplify" it and if parts of it came down to the above, which expression is "simpler"? Depends on the metric. If you are looking for a SOP (Sum-of-Products) representation, then the first is probably as good as it gets. If you are looking for fewest transistors or shortest propagation delay, then the second. There are other metrics that might well yield different solutions, using that metric, are "better".

Turning to this particular circuit, it actually has the same issue. Every AND and OR gate in the circuit with the exception of the 5-input AND that produces the Carry output can be replaced with NAND gates making the overall circuit significantly smaller and faster (assuming a CMOS implementation), but doing so would almost certainly make the logic more convoluted for us humans to grasp from the schematic. So which is "better"? Depends on what you are trying to do. If making circuits to actually accomplish something and turn a profit, you would pick one, but if trying to teach how these circuits perform useful functions, you might well pick the other.

Studying them is a very good start. Study as many different circuits as you can. Learn how an edge-triggered flip flop is actually constructed (and there are three common ways that are markedly different). Learn what adders and multipliers and seven-segment decoders and binary counters and gray code counters are and how they work and what they are used for. The more circuits you have been exposed to and understand, the bigger your toolbox will be when it comes to designing your own circuits.

And design your own circuits. Become a hobbyist. Play with them. Pick a moderately complex project (meaning that it is a bit beyond your current skills) that is of interest to you and dig in. Struggling with the complexity that pushes beyond your present skills is what you will learn the most from and choosing one that is of interest to you will provide the motivation to push through those struggles.

My pleasure. I enjoy helping anyone that is truly willing to put forth the effort to learn.

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10. ### corabict Thread Starter New Member

Dec 29, 2012
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WBahn ...
Thank you very much ..
i was smiling reading ur comment i was very happy & excited of how u explain the meaning of better to me ..
i'll try harder your words inspires me .. & u opened my eyes on some new aspects ..
i can't thank you enough

11. ### bratsuzao New Member

Jan 11, 2013
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Explain what you can about it based on the diagram.