# help completely new to circuits/

#### rainonyourbrain

Joined Sep 13, 2005
1
ok i have been working this problems for quite a while and i'm completely stuck please help! my book is useless!!!

1) use extraction to find a shared, minimum gate input count, multi-level implementations for the pair or functions using AND and OR gates and inverters.
a ) f(a,b,c,d)= ∑ m(0,5,11,14,15), d(a,b,c,d)= ∑ m(10)
B ) g(a,b,c,d)= ∑ m(2,7,10,11,14), d(a,b,c,d)= ∑ m(15)

2)Use elimination to flatten each of the function sets given into a two-level sum of products form
a) F(A,B,G,H)= ABG( bar over the G ) + BG ( bar over B ) + AH(bar over both)
G ( C,D)= CD(bar over D) +CD(bar over C) H(B,C,D)= B + CD

B ) T(U,V,Y,Z)= YZU + YZV(bar over YZ) U(W,X) = W + X(bar over x)
V(W,X,Y) = WY +X(bar over W)

won't let me put the bar over the letter...sorry!

any help/explanations would be GREATLY appreciated!! THANKS!

#### aibelectronics

Joined Aug 26, 2005
24
a ) f(a,b,c,d)= ∑ m(0,5,11,14,15), d(a,b,c,d)= ∑ m(10)
B ) g(a,b,c,d)= ∑ m(2,7,10,11,14), d(a,b,c,d)= ∑ m(15) /quote]

Ha! where did you get these equations from? I can't quite say but it looks wrong. How could there be a don't care on a, b, c and d. Can you clarify.

Anyway, the way to solve this kind of problems is to draw your truth table, make the entries into your karnaugh map, minimise, and implement using logic gate.
good luck!