# Help - Amplifier with BJT and Mosfet

Discussion in 'Homework Help' started by Alfa_ET, Nov 26, 2011.

1. ### Alfa_ET Thread Starter New Member

Feb 26, 2011
17
0
Hi everybody,

I need help in this exercise of electronica. I'm not sure about the results I got. Please see my resolution and tell me where I am wrong.

Exercise:
http://img7.imageshack.us/img7/2826/digitalizar0001pi.jpg

Resolution part 1:
http://img259.imageshack.us/img259/2006/digitalizar0002d.jpg

Resolution part 2:
http://img832.imageshack.us/img832/4278/digitalizar0003v.jpg

Resolution part 3:
http://img12.imageshack.us/img12/3479/digitalizar0004wd.jpg

Resolution part 4:
http://img522.imageshack.us/img522/3710/digitalizar0005im.jpg

Thank you all
greetings

Last edited: Nov 26, 2011
2. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
784
Keep in mind for the PMOS case the source must be at a higher potential than the gate.

You have calculated for the PMOS

Vgs = 3.61V and Vg = 3.64V

Thus Vs2 should be 3.61V above Vg2.

Hence I would think Vs2=3.61 + 3.64=7.25V rather than 0.03V ....

3. ### Alfa_ET Thread Starter New Member

Feb 26, 2011
17
0
Yes you are right. And about Vdrain 2?

4. ### Alfa_ET Thread Starter New Member

Feb 26, 2011
17
0
the gain of first stage is -gm1*Rd. And about the gain of second stage?

5. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
784
I would think the 'logical' thing to do would be to set VD2 [Vo] static bias voltage to 0V or mid-poiint between the ±10 rails. This is an unusual amplifier configuration I've not met before so I would have to look at the circuit more carefully to be convinced in my own mind.

In any case if VD2 is 0V and ID2 ≈ 7.27mA then RL would be 10V/7.27mA=1376Ω.

I also think your estimate for ID1 & RE might be off a little.

One can show for the NMOS

ID≈(gm)^2/(4*Kn)≈(4E-3)^2/(4*2.4E-3)=1.67mA

hence

RE≈0.815/1.67mA=488Ω

6. ### Alfa_ET Thread Starter New Member

Feb 26, 2011
17
0
Why set Vd2 to 0V? maximum excursion of the signal?

7. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
784
That was my reasoning - yes. But as I noted earlier I'd have to take a closer look at the large signal conditions to confirm that supposition.

Last edited: Nov 27, 2011
8. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
784
Did a simulation of the configuration out of interest.

I note that the onset of large signal output cut-off is fairly insensitive to the DC bias operating point of the PMOS drain.

The output THD is ~10% with an input of 400mV p-p.

Peak voltage gain is about 6x with phase inversion.

• ###### MOS-BJT Amplifier Problem.png
File size:
6.1 KB
Views:
22
Alfa_ET likes this.
9. ### Alfa_ET Thread Starter New Member

Feb 26, 2011
17
0
Good work.
RL and RD had given the same value, except RE.
What simulation software do you use?
can you check the output resistance of the amplifier? I think the value is close to the value of RL.
the gain is gm1*RL but i don't know explain why.
thank you

10. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
784
Yes I would think Rout≈RL. The PMOS effectively acts as a current source driver into the load, so looking back into the drain terminal one sees a high AC impedance. That leaves just RL in parallel with a high impedance.

As to the overall voltage gain I think it would be given by

$A_v=-\frac{g_{m1}g_{m2}R_LR_D}{1+g_{m2}R_D}$

which can be approximated by

$A_v=-g_{m1}R_L$

provided

$g_{m2}R_D>>1$

The latter is true in my simulation setup as the apparent gm2 value is much greater than the value of 5mA/V stated in the original problem definition. That's dictated by the PMOS type and its parameters.

Looking at circuit values in my simulation the gm1 value works out around 4.3mA/V and this equates well with the observed voltage gain of 6x. Since |Av|≈gm1*RL=4.3*1.4=6.0