I have a 555 timer that creates what I believe to be a square wave. This 555 timer feeds into a 4 bit counter (only using 3 bits) and from there into two separate 8-1 multiplexers (74LS151).
One of those has bit 0 set to high and the other one has bit 4 set to high.

The two outputs I get create alternating pulses like so:
output a: 10000000
output b: 00001000

Then I use the inverse of output b:

output b: 11110111

Now here is where my trouble starts. For the J-K flip flop I use a 74LS76. I put J, K, and preset to high and clock to output a and clear to output b.

I want to create a perfect square wave with these pulses, such as that I can prevent one of the output b pulses from reaching the flip flop and in that double the period.

when output a goes high, the flip flop starts blinking almost sporadically. Even when I put clear on high, the flip flop is supposed to toggle which each pulse coming from output a but on my board it's toggling more often than this output a signal.

the weird thing is, if i send the clock signal with a parallel port instead of the previous circuitry, then the flip flop behaves as expected. The output toggles with each falling edge of the clock signal.

Could it be possible that the multiplexers sending the pulses are actually sending many pulses or a "rough" type of signal that look like pulses to the eye? I don't have a oscilloscope available right now, hence I'm only guessing.
I'm posting this because I might be missing something obvious, like a capacitor in the right place or another component.

To summarize, everything from the 555 -> counter -> multiplexers is keeping pace until the flip flop, that's acting up.

I can provide a schematic if needed. thanks for any help.

 

Do you have 0.1uF bypass capacitors across the Vcc/GND pins of each of your IC's?
Do you also have a 220uF cap across your 555 timer Vcc/GND pin?

Is your 555 timer CMOS or bjt? (it makes a difference)

Can you post a schematic?

 

The multiplexer will likely produce tiny glitches (a few nanoseconds wide) when ever the counter, running on its inputs, changes more than one bit at a time. Example: when count 0 goes to 1 there is no glitch, when count 1 goes to 2 there is a glitch etc. About half the counts will possibly glitch because the mux sees some bits rising as others are falling.

To fix this you need to use the mux's enable pin and only enable the mux output in between counter output transitions.

A "mickey mouse" fix might be to put an RC filter on the JK FF clock input to filter out the glitches but not the pulse.

Have fun