Hi All,

I am designing a Class D audio amp and started to ask myself what happens at the source of the switching after the top MOSFET switches off (i.e. M1 in the picture).

I have not depicted the bottom MOSFET other than its flyback diode.

My original query was how to size diodes D1 and D2. I was following a reference design from International Rectifier where they seem to have used diodes with an If=1A and an Iffsm=40A.

My original understanding was, that when M1 switches off, a current path through L1 must be maintained to drive the speaker until L1 is discharged of energy. This as I thought naturally comes through D2, which I was correct.

The thing is, D2 sees basically the full load current during upper FET off stage. For the reference design of a 250W @ 50V amplifier, this should be approximately 5-7A. So how could International Rectifier choose diodes which can only sustain 1A continuous? I mean, even if we consider off cycles etc.. etc.. 1A still seems too small.

When I sat down to simulate this, I was caught off guard by the ripple at the source of M1. It appears to be once L1 is primarily discharged of energy. This just seems odd to me and hard to explain. Is this normal? Is it not going to be a huge EMC issue? Although this is just a hobby, any half bridge circuit I work on in the future will be impacted similarly.

Thanks in advance for your interpretations.

James

 

LTSPICEIV simulation attached.

 

Also, I know that MOSFETs have parasitic body diodes. The schottky's will be added as flybacks to improve on the Trr as they are fast switching diodes.

 

D2 is the freewheeling diode and needs to be rated at least for average amps (as you said). The circuit should not be allowed to go into discontinuous mode (the ringing) as you should never let L1 "release its energy". The freq needs to be high enough so the current ripple in L1 is reasonably small, there should be a spec in the design notes from Int Rect, probably about 20% current ripple max?

Now if you are using a bottom FET as well, the 2 FETs work as push/pull where one of the FETs is basically on at all times. So the dissipation of the diodes is almost nothing, they cover the switching deadspace which is probably only 1% or 2% of the total time period. So if your design notes has push/pull drivers then the diodes don't need to be rated for average current.

I think trying to simulate half of the circuit has caused all the confusion?

 

Ok I see.

Actually the confusion came from my misunderstanding half bridge switching. I am used to full-bridge, where yes, either upper or lower FETs are on at any given time.

I was under the impression that for half bridge this was not the case. Luckily I simulated this to consolidate my understanding through confusion.

Now that makes much more sense, and yes, given a 1A diode has a peak forward current rating of 40A, and it must only interact during the 30nS dead band, it should be sufficient.

Thank you for your help.

Since I did raise the topic however, it might be nice to help me understand what I have presented. So basically, given L1 has been discharged and is no longer the 'primary' source of energy as it enters into oscillation, this basically becomes an RLC tank and is resonating?

Cheers

 

D2 is the freewheeling diode and needs to be rated at least for average amps (as you said). The circuit should not be allowed to go into discontinuous mode (the ringing) as you should never let L1 "release its energy". The freq needs to be high enough so the current ripple in L1 is reasonably small, there should be a spec in the design notes from Int Rect, probably about 20% current ripple max?

Now if you are using a bottom FET as well, the 2 FETs work as push/pull where one of the FETs is basically on at all times. So the dissipation of the diodes is almost nothing, they cover the switching deadspace which is probably only 1% or 2% of the total time period. So if your design notes has push/pull drivers then the diodes don't need to be rated for average current.

I think trying to simulate half of the circuit has caused all the confusion?

Please help me also understand this 'discontinous' mode. I was recently looking at a similar effect in a DCM (Discontinuous) flyback converter where once the transformer core is drained of energy, such a resonance occurs on the drain of the primary side from the primary side inductance.

How can I logically tie these two concepts together? Can you help me understand such a phenomenon in flyback converters as I was uncertain how to explain it when I saw it.

Thanks in advance

 

The circuit as a "half bridge" which you first posted is basically a buck converter, you can google heaps of good design notes on buck converter design.

They will also cover "discontinuous mode" which basically is used for low current conditions. Normally the current in the inductor is held pretty constant by using a high enough switching freq. But if your load drops very low, the SMPS goes into discontinuous mode where it just turns on for a short ON pulse with an unknown off time inbetween (determined by load current requirements). Most modern SMPS will do this mode ok, but some systems dont like it (like some PC supplies) and these will have a minimum load current requirement and if that is not met the entire SMPS shuts down.

As for your funky simulation? Who knows what it thinks it's doing? That's the main reason I don't use simulators. Solder a few parts together and hook it up to the CRO man!

 

It is indeed just LC resonance in both situations as there ceases to be an energy source to drive the circuit.

I wonder how much of an EMC impact such resonances have considering there is relatively little power behind it?