Half Adder VHDL help

Discussion in 'Homework Help' started by Prototape, Apr 7, 2011.

  1. Prototape

    Thread Starter New Member

    Feb 12, 2011
    I'm pretty much dead in the water on this. My professor didn't really go over VHDL very much since he didn't want the class to be a coding class. I know the structure of VHDL and I'm fine altering code from the textbook to cover certain things, but when it comes to creating my own code...

    I'm supposed to be creating a VHDL file to program for this half adder:


    I'm lost, and would really appreciate the help.
    Thank you.
    Last edited: Apr 7, 2011
  2. Georacer


    Nov 25, 2009
    There are many levels of implementation in VHDL. Notably the dataflow and behavioural descriptions. They are quite different from each other.

    Care to do a little reading? Check here: http://courses.microlab.ntua.gr/file.php/36/VHDL-intro2.pdf
    Pages 54 and 55 give a close dataflow example. Both pages are required for the code to be complete.

    Basically you first have to declare your system as an "entity", reporting its inputs and outputs and then construct its architecture, following either the behavioural or the dataflow model.
  3. Prototape

    Thread Starter New Member

    Feb 12, 2011
    Considering the chapter in my book covering VHDL is cluttered and isn't really straightforward, this is a big help. Thanks, I'll give this a read.