It is quite simple. In old circuit I have Vss pin and COM pin connected. It's the main reason make this circuit to be not stable. So I decoupled these two ground then this circuit work nicely with variety types of 12-24V motor .

This is what I've found in using the IR2110 also, which is why I keep bringing it up in this type thread. Even though others say that Com and Vss can and should be tied together.

Glad you got it working!

 

should be tied together.

I hope you are not referring to my posts.

According to the app notes it can be connected together, but apparently you are right, it shouldn't. At least not when people are working with such relatively high currents.

Keep bringing it up.

 

I think the problem is that the IR2110 is not really a half-bridge driver. The data sheet says "independent high and low side driver" Also since it is made for up to 500V switching the logic and power are separate. I forget now what forum I saw to keep them separate but on the motor controller I used these on worked after separating them.

Told you I was keeping my eye on you I've learned a lot following you posting. Thanks

 

I think the problem is that the IR2110 is not really a half-bridge driver. The data sheet says "independent high and low side driver" Also since it is made for up to 500V switching the logic and power are separate. I forget now what forum I saw to keep them separate but on the motor controller I used these on worked after separating them.

This OP managed to latchup the low side of the driver. I've personnally experienced the high side doing it and this case is also described in IRs' application notes.

You are right, several times the problem with the 2110 has been solved by separating Vss and COM. As it is the case for the high-side latchup, I'm sure that for other failure modes too (this thread too) some absolute maximum parameter is exceeded. I just don't know which.

I would be curious to know if the problem can ONLY be solved by separating them (needs the additional power supply) or if it can be solved by modifying the layout.

It's remarkable that people always manage to make their circuit work until a certain amperage and then... it fails.

 

Hello, i've try to upgrate my control circuit of H-bridge. Now I use just only 1 PWM signal and 1 direction signal to control my H-bridge. I use the delay circuit in this thread :http://forum.allaboutcircuits.com/showthread.php?t=63183&highlight=deadtime&page=2
. The real PWM signal from this delay circuit is just like the simulation. The inverting signal is used to control Q2 MOSFET(in the layout). The non-inverting for Q1. But my FETs is hot. is the width of the pulse to control Q2 the reason?

 

Hello, i've try to upgrate my control circuit of H-bridge. Now I use just only 1 PWM signal and 1 direction signal to control my H-bridge. I use the delay circuit in this thread :http://forum.allaboutcircuits.com/showthread.php?t=63183&highlight=deadtime&page=2
. The real PWM signal from this delay circuit is just like the simulation. The inverting signal is used to control Q2 MOSFET(in the layout). The non-inverting for Q1. But my FETs is hot. is the width of the pulse to control Q2 the reason?

Please post your schematic again when you do modifications.

How long is the deadtime? Are all 2110 inputs LOW during this time?

Which FET gets hot?

 

I used old circuit and build delay circuit in breadboard. The deadtime is about 8 us. all the inputs are LOW for sure. 3 FETs used are hot(Q1,Q2,Q4).
<a href="http://s297.photobucket.com/albums/mm230/phongkem/?action=view&current=1.jpg" target="_blank"><img src="http://i297.photobucket.com/albums/mm230/phongkem/1.jpg" border="0" alt="Photobucket"></a>

 

 

frequency is about 500Hz and I use a 10uF electrode cap paraell with a 10uF ceramic cap

 

frequency is about 500Hz and I use a 10uF electrode cap paraell with a 10uF ceramic cap

Where in your circuit is this?

In the other post you linked to the original circuit. Didn't you make modifications? It's hard to take part of the circuit from here, then the other part from another thread etc. to understand how your circuit looks like.

Are you sure the problem is related to the deadtime circuit?. Did it work before?

 

Where in your circuit is this?

C5 and C6 in the layout
I didn't make any modification to the H bridge( of which I post the layout).
It still work well with seperate PWM signals. i.ein flowing pic) Pwm signal1 = Pwm signal4, Pwm signal 2 delay from Pwm signal1 8us and have a width = 24us.

I found out that If I increase the width of pwm signal2 just like the delay circuit the FETs get hot too. So did the width of charging pulse make the effect to the FETs ?

 

How is Q3 driven?

 

I have just tested in one direction. Q3 in this case is driven by a Low signal to Lin.

 

Can you post the actual schematic?

In the schematic of your first post, where is C6?

Maybe there is not enough time to fully charge the bootstrap capacitors. At what voltage level is the gate signal for the upper MOSFETs?

 

This is my schemantic for 1/2 H-bridge along with the layout I have posted

I don't think the bootstrap cap is not fully charge because, with the same this circuit when I used old style of control, the pulse width is just 16us but now the width is even bigger.

 

Ok, according to your picture the deadtime is the same, PWM frequency is the same, the only thing that changed is the pulse width.

You are right the bootstrap cap voltage should be equal or better than before, I would just check it. All gate pulses should have the proper voltage levels.

If the picture is correct then only thing that really changed is the time the transistors remain switched on. There would be a higher dissipation due to the RDSon.

You should post scope pictures of Vgs of all MOSFETs.

Do the transistors have a heatsink? What size is C7?

 

Is the bootstrap capacitor sized correctly for the mosfet gate? When changing the time of the pulse the boot cap must supply enough voltage for the increased "time on", or the Vgs will start to drop and the mosfet will start into the "linear region" increasing heat in it.

 

@praondevou: I will post scope pic latter.
@shortbus: I use the equation in application note to calculate. You can see in the pic, the old style use less time to charge the cap but it work well so It make me very confused.

 

c7 = 47uF, and FETs don't have heat sink(I think it's no need to have heat sink here because it worked well without it)

 

c7 = 47uF, and FETs don't have heat sink(I think it's no need to have heat sink here because it worked well without it)

Ok if you say it worked before without heatsink I'll have to believe it. I would nevertheless think that at 20A nominal current (+ PWM) I would NEED a heatsink, only RDSon would account for more than 3W power dissipation in each MOSFET. Add switching losses to that.