Grounding the negative input of a differential mode ADC pin

Thread Starter

SiCEngineer

Joined May 22, 2019
337
Hi,

I am designing a power supply which requires a very low voltage ripple at the output. I worked out that to achieve the level of ripple required the ADC must have at least 16 bits. I am using the F2837xD Microprocessor which can work in either 12-bit "single-ended" mode or 16-bit differential mode. I have seen multiple sources online say that it is possible to use differential mode inputs even for ground referenced signals by connecting the negative differential input to the analogue ground. When looking through the data sheet, TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual (Rev. I) (ti.com) Page 1560, it shows the configuration of the differential inputs of the ADC.

My question is, if I was to ground the negative input of the ADC in differential mode, would this be acceptable, or would it cause issues? My concern is obviously that grounding the negative terminal will short out the lower capacitor. See image below:

1631810475852.png
I am planning on using oversampling and interleaving of the ADC's but it is still not enough when using the single-ended ADC mode with only 12-bits of resolution.

Any comments welcomed.

SIC
 

nsaspook

Joined Aug 27, 2009
8,904
You can get 16-bit results with Differential mode but don't bet on actually using all of that 16 bits with a SE source signal. Sure, you can connect the - input to analog signal ground. Just check your zero-offset calibration trim with a zero input signal on the + pin.
 

Thread Starter

SiCEngineer

Joined May 22, 2019
337
You can get 16-bit results with Differential mode but don't bet on actually using all of that 16 bits with a SE source signal. Sure, you can connect the - input to analog signal ground. Just check your zero-offset calibration trim with a zero input signal on the + pin.
So in your opinion, from the physical structure of the differential inputs shown above, connecting one end to ground won’t cause any issues on the DSP?

What is a more realistic expectation for the resolution in bits when using a SE source in a differential ADC? Are we talking 15 or are we talking 12, at which point there’s not much point anyway?
Is there a reason why you cannot achieve the specified resolution when it is used in this way?
 

nsaspook

Joined Aug 27, 2009
8,904
So in your opinion, from the physical structure of the differential inputs shown above, connecting one end to ground won’t cause any issues on the DSP?

What is a more realistic expectation for the resolution in bits when using a SE source in a differential ADC? Are we talking 15 or are we talking 12, at which point there’s not much point anyway?
Is there a reason why you cannot achieve the specified resolution when it is used in this way?
No it won't cause a physical device problem being grounded. What I'm saying is don't expect the full 16-bits to be usable as a stable result in this configuration.
https://www.analog.com/en/analog-di...-for-high-speed-differential-adc-drivers.html
Most modern high-performance ADCs use differential inputs to reject common-mode noise and interference, increase dynamic range by a factor of two, and improve overall performance due to balanced signaling. Though ADCs with differential inputs can accept single-ended input signals, optimum ADC performance is achieved when the input signal is differential.
 

crutschow

Joined Mar 14, 2008
28,201
I am designing a power supply which requires a very low voltage ripple at the output. I worked out that to achieve the level of ripple required the ADC must have at least 16 bits
How do you intend to use the ADC to reduce ripple?
Power supply ripple is normally determined by the output filter.

Or are you referring to output voltage adjustment resolution.
 

Thread Starter

SiCEngineer

Joined May 22, 2019
337
How do you intend to use the ADC to reduce ripple?
Power supply ripple is normally determined by the output filter.

Or are you referring to output voltage adjustment resolution.
I do believe the second point is what I mean. The ripple will be less than 100mV after the capacitors and the second-stage filter that I have designed. This much is fine. However, I also need to regulate this voltage very accurately. With an output voltage of say 600V and a ripple of 10mV, this requires 60,000 levels of representation. Using the 2^N equation for number of bits, this requires 16 bits which allows 65,536 levels. The single ended ADC is only 12 bits so only allows 4096 levels.
 

nsaspook

Joined Aug 27, 2009
8,904
While in theory you have 16 bits of control, in an actual circuit that's unlikely to be usable to the resolution you need. For something like this you will likely need at least a few more bits in the measurement system for stability and noise reduction with a very good VREF standard.

https://forum.allaboutcircuits.com/threads/50nv-resolution.130468/post-1073894
https://forum.allaboutcircuits.com/threads/super-moon-shine.100322/post-899878
From the program info header:
* A special version for the TI ADS1220 SD ADC converter chip (and MCP3911 later) for low voltage sensing and
* solar panel panel light detection. +- 2.048, 1.024 and 0.512 voltage ranges @ 20 bits of usable resolution
* ADC is in single-shot conversion mode @20SPS, PGA disabled and gain from 1, 2 and 4 in differential
* signal detection mode, 50/60Hz rejection enabled. 500kHz SPI clock with direct RPi connection
* Analog +- 2.5VDC from Zener regulators for the bipolar input stage with external 2.5VDC Zener input
* signal protection.
 

Thread Starter

SiCEngineer

Joined May 22, 2019
337
While in theory you have 16 bits of control, in an actual circuit that's unlikely to be usable to the resolution you need. For something like this you will likely need at least a few more bits in the measurement system for stability and noise reduction with a very good VREF standard.

https://forum.allaboutcircuits.com/threads/50nv-resolution.130468/post-1073894
https://forum.allaboutcircuits.com/threads/super-moon-shine.100322/post-899878
Very impressive work. Unfortunately the ADC on the control board I am using is maximum 16 bits for the differential mode. There are however 4 ADCs on the board and each has 16 channels - I was thinking there may be a way to interleaved the measurements and oversample the signal alongside the 16-bit measurements. That may bump up the resolution by about 1 bit only. The other solution could be to have an external 20 bit ADC like you state, and use the DSP board for everything else like the rest of the measurements and fault detection, and gate drive outputs.
by a stable Vref, do you mean that rather than attaching the negative input of the differential amp to ground, you connect it to a very well regulated constant voltage derived possibly from a regulator and voltage divider? Does that then allow more accuracy with the 16-bit differential mode?
 

nsaspook

Joined Aug 27, 2009
8,904
By Vref I mean the ADC reference used to measure the unknown input voltage with. It can internal or external. Every source of noise and drift must be accounted for that level of usable resolution. Do you really need that fine voltage adjustment resolution?
https://www.ti.com/lit/eb/slyy192/slyy192.pdf?ts=1631892673282

At 16 bits that's 0.001526% full span, 15.26ppm. That 24-bit external Delta-Sigma ADC I used has a Internal 2.048-V Reference: 5 ppm/°C (typ) Drift. A similar quality external Vref for your microcontroller would be something like this: https://www.ti.com/lit/ds/symlink/ref3230.pdf
 

Thread Starter

SiCEngineer

Joined May 22, 2019
337
By Vref I mean the ADC reference used to measure the unknown input voltage with. It can internal or external. Every source of noise and drift must be accounted for that level of usable resolution. Do you really need that fine voltage adjustment resolution?
https://www.ti.com/lit/eb/slyy192/slyy192.pdf?ts=1631892673282

At 16 bits that's 0.001526% full span, 15.26ppm. That 24-bit external Delta-Sigma ADC I used has a Internal 2.048-V Reference: 5 ppm/°C (typ) Drift. A similar quality external Vref for your microcontroller would be something like this: https://www.ti.com/lit/ds/symlink/ref3230.pdf
Yes, the voltage resolution is the primary concern for the specification. The voltage itself can move +/-5V but unfortunately the actual ripple superimposed on this has to be less than 0.0017% which obviously is a tricky thing to achieve.

I could use LTC2401/LTC2402 - 1-/2-Channel 24-Bit µPower No Latency Delta-Sigma ADC in MSOP-10 (mouser.co.uk) , alongside the voltage reference https://www.ti.com/lit/ds/symlink/ref3230.pdf that you proposed. The DSP that I have is the F2387xD TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual (Rev. I) (ti.com) which has an SPI interface - the 24-bit ADC I have sent above also can communicate with SPI.

Does this sound like a solution? Will the performance be limited by the DSP ADC clock? It is I think 50MHz or so, so I dont envisage there wil be any problems there? Anything else I should be cautious of using this technique? From the data sheet

" The SPI module on this device has a high-speed mode that enables 40 Mbps communication. To achieve the highest possible speed, a special GPIO configuration is used on a single GPIO mux option for each SPI. These GPIOs may also be used by the SPI when not in high-speed mode (HS_MODE = 0). shows which GPIOs have the special mux option to allow SPI high-speed mode. "

But one of my concerns is that the "conversion time" for the ADC is in the hundreds of milliseconds range, which is most likely way too slow. External oscillator maximum is less than 500Khz whereas my clock is 50MHZ, so no point there. Is it typical that if you have high resolution, you are unable to get high sample rate? Mutually exclusive?

Regards,SIC
 
Last edited:

nsaspook

Joined Aug 27, 2009
8,904
But one of my concerns is that the "conversion time" for the ADC is in the hundreds of milliseconds range, which is most likely way too slow. External oscillator maximum is less than 500Khz whereas my clock is 50MHZ, so no point there. Is it typical that if you have high resolution, you are unable to get high sample rate? Mutually exclusive?

Regards,SIC
That's the nature of the beast. There are faster parts: https://www.ti.com/lit/ds/symlink/ads127l01.pdf?ts=1632074478473
 

Thread Starter

SiCEngineer

Joined May 22, 2019
337
That's the nature of the beast. There are faster parts: https://www.ti.com/lit/ds/symlink/ads127l01.pdf?ts=1632074478473
Yes, I happened to find a 2.5MSPS one from Linear tech but it is only 18 bits. These must be the extremes of the devices.

I have looked at my DSP and the SPI interface that can communicate with an external ADC only has 16 bits of data on it. Do you have any recommend for how best to communicate a 24-bit signal with a 16-bit interface? The Linear technology one I have found has separate pins foreach output of the 18bIt ADC, so I could process them with individual GPIO pin reads to form a 18-bit word, but I would be open to hearing other suggestions.

would a 24-bit sub 1MSPS ADC be superior to a 18-bit 2MSPS for my application? The output voltage ripple will be at approximately the converter switching frequency or higher which is 1MHZ so I would be worried of information loss sine it is below twice the Nyquist.
 

nsaspook

Joined Aug 27, 2009
8,904
It's usual to transfer 32-bits for a 24-bit ADC spi result. With a 16-bit interface two transfers will clock all data, with an 8-bit interface it would take 4 transfers so that's usually not a problem with high SPI clock speeds.
 
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