Ground and 0V source acting different in LTspice

Thread Starter

samihawasli

Joined Oct 19, 2020
10
NOTE: this should probably be under the PCB Layout , EDA & Simulations forum, sorry..


Hello all,
I am sure I am missing something fundamental about LT-spice, but I made a very simple d-flip flop (FF) ctk, and it wasn't acting as expected. I need D to present logic low, in order to set the output low on the clock's rising edge. However, when I ground the D input to the FF, the circuit responds different than when I put a 0V DC source on the D input.
1605037465812.png
Above is the case with the 0V source connected to D. At the start of the simulation, a short pulse on Vset set the FF's output high. Upon the clock's first rising edge the FF output goes to zero, as expected.
1605037674853.png
Above is the case replacing the 0V source on the D input with a ground connection. Now the FF output gets set in the intial set pulse, then remain high regardless of the clock.
1605037854224.png
This phenomenon doesn't seem to affect the CLR input the same way. Any ideas what I am missing here.
Thanks in advance,
Sami
 

crutschow

Joined Mar 14, 2008
27,004
There is a blue dot on the D input which indicates a dangling connection.
Eliminate that and see if you still have a problem.
 

Thread Starter

samihawasli

Joined Oct 19, 2020
10
There is a blue dot on the D input which indicates a dangling connection.
Eliminate that and see if you still have a problem.
Thanks for the reply! I got the same results, I just had a bit of wire extended past the D connection.
1605040477712.png
working case above with 0V source. Not working case with grounded input below
1605040602871.png
Thanks again.
 

eetech00

Joined Jun 8, 2013
2,318
NOTE: this should probably be under the PCB Layout , EDA & Simulations forum, sorry..


Hello all,
I am sure I am missing something fundamental about LT-spice, but I made a very simple d-flip flop (FF) ctk, and it wasn't acting as expected. I need D to present logic low, in order to set the output low on the clock's rising edge. However, when I ground the D input to the FF, the circuit responds different than when I put a 0V DC source on the D input.
View attachment 221932
Above is the case with the 0V source connected to D. At the start of the simulation, a short pulse on Vset set the FF's output high. Upon the clock's first rising edge the FF output goes to zero, as expected.
View attachment 221933
Above is the case replacing the 0V source on the D input with a ground connection. Now the FF output gets set in the intial set pulse, then remain high regardless of the clock.
View attachment 221934
This phenomenon doesn't seem to affect the CLR input the same way. Any ideas what I am missing here.
Thanks in advance,
Sami
Hi...yes...confusing...but not a bug. This one fools a lot of LTspice users.

The native LTspice digital gate behavior is different than one would expect.
When an input is connected directly to ground (like with an LTspice ground symbol), LTspice treats it as an unused pin and eliminates the pin from the circuit. So its basically ignored. Unused pins should be left unconnected. If you need an input to be active, pull it high, or low (with a resistor), or connect it to another component. The A devices aren't really intended to be used in their raw form, but to be encapsulated with other devices to form a complete logic function.

Some of this is described in the LTspice Help.

Hope that helps...
 
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