I have a debouncing circuit using the MC14490. It is not working, and I am looking for some help in interpreting the datasheet.
In the datasheet, the active input should have a pull-up resistor, with the switch connected to ground. The oscillator input and output should be connected with a capacitor. I have the MC14490 connected up as shown in the datasheet, but when I close the switch a) the input pin does not go Low, and b) the output pin also does not go Low but c) the low side of the pull-up resistor does go Low (and the circuit works if I connect it up without the MC14490).
My Vdd is 3.3.V. I am using a 101 100pF capacitor to connect the oscillator input and output, and I have confirmed with a probe that the oscillator is working.
In the datasheet, the IC is described as 3 V-18 V, but all the switching values are give at 5, 10 or 15 V. At 5 V my 100pF capacitor would give a frequency of 15 KHz if I have read the datasheet correctly.
My questions are:

• What would be a "typical" value for the oscillator capacitor in a 3.3 V circuit?
• What do the "typical" and "max" oscillator values mean? Do they mean that a frequency of 2.8 MHz is typical and a frequency of 1.4 MHz is the Maximum (minimum?)?
• What does the statement on page 6 mean: "Because of the built−in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V."

Any help on this is much appreciated,

 

In the datasheet, the active input should have a pull-up resistor, with the switch connected to ground. The oscillator input and output should be connected with a capacitor. I have the MC14490 connected up as shown in the datasheet, but when I close the switch a) the input pin does not go Low, and b) the output pin also does not go Low but c) the low side of the pull-up resistor does go Low (and the circuit works if I connect it up without the MC14490).
My Vdd is 3.3.V. I am using a 101 100pF capacitor to connect the oscillator input and output, and I have confirmed with a probe that the oscillator is working.
In the datasheet, the IC is described as 3 V-18 V, but all the switching values are give at 5, 10 or 15 V. At 5 V my 100pF capacitor would give a frequency of 15 KHz if I have read the datasheet correctly.
My questions are:

• What would be a "typical" value for the oscillator capacitor in a 3.3 V circuit?
• What do the "typical" and "max" oscillator values mean? Do they mean that a frequency of 2.8 MHz is typical and a frequency of 1.4 MHz is the Maximum (minimum?)?
• What does the statement on page 6 mean: "Because of the built−in pullup resistors, the inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V."

Any help on this is much appreciated,

The chip appears to have internal pullups.
The 2 sections highlighted seem contradictory. Could you clarify?

I would make the oscillator cap at least 100x larger to make the oscillator run at a much lower frequency. 15khz seems too high to get enough successive clean clock signals for the chip to operate as intended. (if I'm understanding it correctly)

Maybe some one has an answer for the MHZ external oscillator spec.

 

Hi,
Yes, the chip has internal pullups.

The datasheet also shows an external pullup on the active input pin. I have a 10k resistor there. The downstream side of the resistor goes Low when I press the switch (this would give me a normal un-debounced switch if I removed the MC14490).

I will try a different capacitor. I already tried different values, but I realised that I do not understand the datasheet on this. The switching characteristics on page 4 give a "typ" value for the clock frequency of 2.8 MHz, and a "max" value of 1.4 MHz. The example described further down uses a 1uF capacitor at 15 V, which with their formula gives 6.5 Hz!

The datasheet says on page 5 that the only requirement is that four clock periods
do not occur while the input signal is in a false state. If I guess that my switch bounces for 5-10 ms, then this would require a clock not faster than about 2 KHz.

The other side of this is that the datasheet does not give values for 3 V, and says that inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V, so I am wondering if it does not work at 3 V at all, or if that refers to something else.

 

I have rtied a 104 0.1uF capacitor and that also does not work. My probe detects that it is oscillating, but the input pin does not go Low.

 

I think you are doing this, but your switch is connected between the input and Gnd correct?
Do you have a 0.1uf bypass cap connected between V+ and ground close to the chip?

Your last post says again the input pin is not going low. Do you mean input or output ?

If no luck, double check your wiring and try the other inputs/outputs, then maybe try a 5 volt supply.
If this is on a breadboard make sure the wires are short.

And last, post a schematic of your actual circuit including what the output is connected to.

Edit: If your switch is bouncing for 5-10 ms the period equates to more like 200hz or 100hz

 

Schematic attached.

The switch is connected between input and ground. I don't have a bypass cap at the moment.

The output pin goes to the second IC input.

My probe tells me the oscillator is oscillating. I currently have a 0.01uF cap, which if I am reading the datasheet correctly should be giving me slower than 100 Hz.

What I meant was that, I should see a debounced Low on the output pin, but I am not seeing it. I think I should also see a bouncing Low on the input pin, but I am not seeing that either, which led me to question what they mean by "inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V".

I tried at 5 V anyway, but no change. I am not clear if it is supposed to work at 3.3 V or not.

 

Well, I think you might want to check your schematic against the chip's pin out
And what is the 2nd IC ?

 

Are you referring to the pin numbering, or something else?
The MC14490 has 16 pins (six debouncers) but I have only shown 8 pins for simplicity.
The second IC is a GPS with an interrupt pin. This works fine if I just connect it to the + side of the switch, but at that point it is not debounced, which is why I am adding the MC14490.

 

It's customary to post a schematic with the actual pin numbers and connections.

It helps us to help you.

Please post the actual schematic, pin numbers and chip number for the GPS chip.

Thanks.

 

Thanks for your help, much appreciated.

You were spot on with the decoupling capacitor. I have added it and now the output pin goes Low as expected. It works at 3 V and 5 V.

I'm afraid I only did a quick schematic in answer to your original question. This is a simple breadboard to try the MC14490. I was unclear about the datasheet, hence my questions. I am now using a 0.01uf capacitor for the oscillator, but the formula they give only goes down to 5 V and appears to be a log scale, so I don't know what frequency that gives.

I am guessing now that the bit about "inputs cannot be driven with a single standard CMOS gate when VDD is below 5 V" may be referring to the oscillator inputs in a multi-MC14490 setup (as illustrated).

 

Great you got it working!

Those pesky decoupling caps are especially important in circuits containing an oscillator or switching circuits and are very frequently left out of schematics.

Check this out:
[thread=45583]Bypass Caps[/thread]


Now it would be interesting to experiment with smaller oscillator caoacitors to determine the range of frequencies that work.

 

Thanks, I had read that Sticky, but somehow thought that it would apply to a more complex circuit, and not just to the one chip. I know differently know, and have read it again.

The oscillator frequency is an odd one. It says that "The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state". A false state is each pulse before it settles. It seems impossible to guess how long one pulse might last. On the other hand, if you take the whole bounce period of say 5-10 ms, then this would cause a longer delay in responding to the signal. I suppose another way of looking at it is that the signal needs to be low for four clock periods before it is considered truly low.

I will try a few different frequencies and see what I get. My main aim is to respond to an input as quickly as possible, but to suppress subsequent (rather than previous) bouncing. I am testing an SPDT circuit for this as well.

 

Thanks, I had read that Sticky, but somehow thought that it would apply to a more complex circuit, and not just to the one chip. I know differently know, and have read it again.

The oscillator frequency is an odd one. It says that "The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state". A false state is each pulse before it settles. It seems impossible to guess how long one pulse might last. On the other hand, if you take the whole bounce period of say 5-10 ms, then this would cause a longer delay in responding to the signal. I suppose another way of looking at it is that the signal needs to be low for four clock periods before it is considered truly low.

I will try a few different frequencies and see what I get. My main aim is to respond to an input as quickly as possible, but to suppress subsequent (rather than previous) bouncing. I am testing an SPDT circuit for this as well.

 

Thanks, I had read that Sticky, but somehow thought that it would apply to a more complex circuit, and not just to the one chip. I know differently now, and have read it again.

The oscillator frequency is an odd one. It says that "The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state". A false state is each pulse before it settles. It seems impossible to guess how long one pulse might last. On the other hand, if you take the whole bounce period of say 5-10 ms, then this would cause a longer delay in responding to the signal. I suppose another way of looking at it is that the signal needs to be low for four clock periods before it is considered truly low.

I will try a few different frequencies and see what I get. My main aim is to respond to an input as quickly as possible, but to suppress subsequent (rather than previous) bouncing. I am testing an SPDT circuit for this as well.

 

...

The oscillator frequency is an odd one. It says that "The only requirement on the clock frequency in order to obtain a bounce free output signal is that four clock periods do not occur while the input signal is in a false state". A false state is each pulse before it settles. It seems impossible to guess how long one pulse might last. On the other hand, if you take the whole bounce period of say 5-10 ms, then this would cause a longer delay in responding to the signal. I suppose another way of looking at it is that the signal needs to be low for four clock periods before it is considered truly low.

I will try a few different frequencies and see what I get. My main aim is to respond to an input as quickly as possible, but to suppress subsequent (rather than previous) bouncing. I am testing an SPDT circuit for this as well.

Yes I agree, the oscillator spec is very odd. ... Not the first time a datasheet is ambiguous, incomplete......

If the switch takes about 5ms max. to stop bouncing, then as you point out a clock period should logically last longer than the longest bounce period to ensure an accurate detection which implies a frequency on the order of 50 hz.

But, what if the frequency was much faster?? Then I think it could easily detect a four clock 'stable' state between bounces, and give multiple false outputs. Not so good..

Glad you mentioned trying an SPDT configuration also. You might get a faster, but still reliable response.

EDIT: Ok... PLEASE forgive me, but it seems the 'Post Reply' button needs a debounce circuit too,

 

The problem with the Post Reply is that it can take more than a few minutes to compose a reply, e.g. while checking a data sheet. After a few minutes it times out, but when you click Submit again it does not appear to respond.

 

The problem with the Post Reply is that it can take more than a few minutes to compose a reply, e.g. while checking a data sheet. After a few minutes it times out, but when you click Submit again it does not appear to respond.

I've noticed recently that the site seems to be slow to respond when posting, I thought it was just my PC. I wonder if others are having similar issues.

 

Reopening this thread for a bit more info. It also seems to say on page 6 of the datasheet:

Because of the built−in pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is
below 5 V. At this voltage, the input should be driven with
paralleled standard gates or by the MC14049 or MC14050
buffers.

If I'm looking at this correctly, using a 3.3V circuit requires the use of a buffer prior to the MC14490. The OP seems to be working fine below 5V with the addition of the decoupling capacitor, but I'm wondering how much value there is to having the buffer prior. Any experience with this?

It's customary to post a schematic with the actual pin numbers and connections.

It helps us to help you.

Please post the actual schematic, pin numbers and chip number for the GPS chip.

Thanks.

And also for people searching for help. We all hate when different people ask the same question on forums when the solution can easily be found in search. Conversely, when we do say SEARCH, we expect the correct answer to be there. The original schematic is incorrect and misleading.

To the OP, why would you put a capacitor between pins 3 and 5 in your reduced schematic? The chip comes in multiple packages, but all have the same pinout. 3 and 5 are pins Cin and Ein on the actual chip. Are you trying to represent a capacitor across pin 7 (OSCin) and pin 9 (OSCout). This is unclear and I'm looking to clarify.