Generating a truth table in Verilog

Discussion in 'Homework Help' started by tempneff, Feb 24, 2013.

  1. tempneff

    Thread Starter New Member

    Aug 11, 2012
    I have been assigned a simple circuit to produce in Verilog using Quartus software 9.1. I have the circuit completed and but I can't figure out how to print all the required results. I was instructed to 'obtain the truth table and timing diagram' I printed the timing diagram, but where is the truth table...
  2. panic mode

    Senior Member

    Oct 10, 2011
    you can create counter of sufficient size to drive all circuit inputs, then your timing diagram will be just another representation of truth table.
  3. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
    How did you write the function in Verilog (did you use the 'table' keyword)?

    What is your testbech code, does it cycle through all inputs?
  4. tempneff

    Thread Starter New Member

    Aug 11, 2012
    This was a simple tutorial where we wrote only this small code and were supposed to just compile and then print. He handed out step by step instructions, but stopped after generating a waveform.

    Code ( (Unknown Language)):
    1. module ece204one(a,b,c,f);
    2. input a,b,c;
    3. output f;
    4. wire y0,y1;
    5. not(y0,c);
    6. and(y1,b,y0);
    7. or(f,y1,a);
    8. endmodule
  5. tempneff

    Thread Starter New Member

    Aug 11, 2012
    For prosperity's sake, to obtain a truth table, i was supposed to save the waveform as a .tbl. This file can be opened in a text editor.
  6. Brownout

    Well-Known Member

    Jan 10, 2012
    It sounds to me like you answered your own question. If by saving the waveform as .tbl creates a table that can be opened in a text editor, then you're done. Otherwise, ask the instructor how to do it. I've never done any such thing.