Hi, im studying for an exam and I need help. Im pretty new to this subject and this forum so I apologize if i do something wrong.

The question is talking about gate level and design. Question A you must illustrate a logic diagram with NAND 00; OR 01; EX-OR 10 ;ADD 11.

Question B is where I am stuck, it asks for other ways of implementing several bit stages to implement the same functions and speak of the advantages and disadvantages for each.

I know the more gates in a sequence the slower and more expensive it is, as you put more gates on the silicon which is expensive.

Any others?
Thanks in advance.

 

If you are putting gates on silicon (i.e., talking IC design) and if it is a CMOS process, you have the option of implementing the logic equations directly in CMOS instead of using traditional gates. This has the advantage of, generally, the smallest footprint, lowest power, and highest speed. But it is a custom design meaning it takes time to design, layout, and verify.

You also have the option to use a look-up table for your logic (this is how most FPGA logic is implemented).

If you are dealing with traditional gates, you can frequently use 'bubble logic' to minimize the gates delays, footprint, and area but generally make the logic function being executed more obscure and, therefore, more difficult to verify and maintain.

 

I know the more gates in a sequence the slower and more expensive it is, as you put more gates on the silicon which is expensive.

Any others?
Thanks in advance.

That should about cover it. Speed, size and cost are the major factors. Other effects are more noise, current consumption, heat to dissapate power decoupling requirements, etc.