Hello,

I have been designing a full bridge single phase inverter. It's bus voltage is 20Vdc. There is enough of dead-time for Vgs signals between the-same-leg mosfets and they are driven by gate driver. I checked Vgs signals for the-same-leg mosfets and saw the dead-time clearly. At each power mosfet turn off moment there is ringing in the bus voltage. Moreover, drain source voltage of each mosfet has %100 overshoot.

If there is a shoot-through problem, which could led bus voltage to collapse for short period of time, why would it occur in my design? I already have dead-time between Vgs signals.

Does anybody have any idea why? If you need more info, please tell me. I can upload some scope pictures if you need.

Thank you for your time
Alper

 

schematic and scope traces, else we're blind...

 

I attached below scope views and schematic. Main issue here is that while drain source voltage changes state, bus voltage collapses in that very instant.

 

It could be the power section layout is spreading out and creates lot of leakage inductance coupling with interwinding capacitance and cause bus ringing during turn off. Check your layout and repackage the power path as close as possible. Second, check the MOSFET gate resistor, too small resistor will cause fast turn off and generates lot of ringing. Reduce Rg could help. Measure the Transformer leakage inductance, redesign if needed to reduce L leakage.

 

Whats your PCB layout for driver and MOSFET stages? As said, layout is critical and can inject transients where you least expect...

 

It could be the power section layout is spreading out and creates lot of leakage inductance coupling with interwinding capacitance and cause bus ringing during turn off. Check your layout and repackage the power path as close as possible. Second, check the MOSFET gate resistor, too small resistor will cause fast turn off and generates lot of ringing. Reduce Rg could help. Measure the Transformer leakage inductance, redesign if needed to reduce L leakage.

What do you refer to by saying transformer? I do not have a transformer in schematic. Gate resistor is 10 ohm at the moment. Leakage inductance along the power lines may be resonating with mosfet output capacitance. Power bus is resonating at 30MHz. 4.7nF ceramic capacitor(lowest impedance at 30MHz) placed across bus could solve it right? I will give it a try.

 

Whats your PCB layout for driver and MOSFET stages? As said, layout is critical and can inject transients where you least expect...

It could be lay-out section causing problems, you are right. But before this, we need to make sure this problem is not about the design.

 

Below is a Full-Bridge simulation result. Vgs signal name indicates mosfet's gate-source voltage while Vds signal name indicates drain-source voltage of two mosfets in the same leg.

My question is that drain-source voltages of two mosfets change states simultaneously irrespective of dead time between Vgs1 and Vgs2. This simultaneos state change of Vds voltages could be causing shoot-through problem. Maybe that's why bus voltage resonates. Any ideas?

 

If the scales are correct the gate voltages are 1v? and the dead time is around 500nS, though those traces are obviously sanitised. What devices are TR0501 through TR0504? Datasheet please.

 

Gate voltages are 15V in reality. 1V is enough to turn mosfet on in simulation. Dead time is 200ns. I will send you datasheets tomorrow morning.

 

What do you refer to by saying transformer? I do not have a transformer in schematic. Gate resistor is 10 ohm at the moment. Leakage inductance along the power lines may be resonating with mosfet output capacitance. Power bus is resonating at 30MHz. 4.7nF ceramic capacitor(lowest impedance at 30MHz) placed across bus could solve it right? I will give it a try.

Please post a full schematic. I assume you are driving FET with SPWM pulse signal at some high frequency (?). The DC power source is either 160Vdc or 310Vdc through a Full Bridge Inverter. And the output will connects to a LV Filter circuit to form a pure sinusoidal voltage ? FET VGS voltage has to be around 12V to ensure full saturation. Putting 1V-2V will cause FET go in linear mode. Do not overlap VGS between FET

 

If the scales are correct the gate voltages are 1v? and the dead time is around 500nS, though those traces are obviously sanitised. What devices are TR0501 through TR0504? Datasheet please.

Attached is the mosfet datasheet for full bridge mosfets.

 

Please post a full schematic. I assume you are driving FET with SPWM pulse signal at some high frequency (?). The DC power source is either 160Vdc or 310Vdc through a Full Bridge Inverter. And the output will connects to a LV Filter circuit to form a pure sinusoidal voltage ? FET VGS voltage has to be around 12V to ensure full saturation. Putting 1V-2V will cause FET go in linear mode. Do not overlap VGS between FET

As you have guessed I am driving FET with SPWM pulse signal at 50kHZ. DC power source is 30V for now. There is LC filter at the output to form pure sine wave. FET VGS voltage is 15V for all FETs. There is clear dead time between same leg FETs.

 

I enhanced DC voltage ripple by placing some 4.7 nf ceramic capacitors betweeen DC bus voltage and ground. However, I have 7-8 watts of loss in snubber circuits. It means that there is great leakage inductance in the circuit which causes that much of power loss. Any recommendations?

Thank you in advance.