hello,

I'm working on a Subway Turnstile FSM project in my digital logic class, and i'm trying to determine if I'm on the right track. It's designed after a NYC Subway Turnstile using Unlimited or Prepaid metrocards. After swiping a prepaid card it deducts from the current balance, and after swiping a monthly, it verifys the expiration date.

I want to make sure that this makes sense logically so I could start writing this in verilog. Any suggestions would be greatly appreciated.

Thanks in advance.

 

What is your PUSH input?

 

What is your PUSH input?

its the transition of passing through the turnstile. any suggestions? perhaps i should rename it as "pass".

 

Then what does it mean when you "push" from the locked state? How did something pass through the turnstile?

What does it mean to "push" through the turnstile and go directly from the "verify" state to the "locked" state?

You need to be very clear and explicit on exactly what your inputs are and what they mean. Otherwise you are going to get your implementation completely messed up because you are needing the same signal to mean different things to different blocks at different times.

 

thanks for the response.

the push input was a mistake, I corrected it.

the description of the fsm is:

"The Subway Turnstile will accept both prepaid and unlimited passes. If a passenger attempts to pass through with anything but a valid card, the turnstile will remain in the locked state. When a passenger swipes a valid card, the FSM will move to the verify state. If an unlimited pass is verified the FSM will move to the unlocked state. If a valid prepaid pass is swiped the FSM will move to the deduct balance state and the proper amount will be deducted from the prepaid pass balance and then move to the unlocked state. Once unlocked the machine will let the passenger pass through and reset back to the locked state. Our design incorporates a Moore Machine where the output depends on the current state."

I'm also having a bit of trouble with creating the verilog. I'm not very experienced with writing verilog and I'm unsure of what my errors are.


module fsm (
input invalid,
input prepaid,
input unlimited,
input insufficient_fare,
input clk,
input rst,
output reg [1:0] state
);

reg [1:0] next_state;

parameter [1:0] FIRST = 2'b00;
parameter [1:0] SECOND = 2'b01;
parameter [1:0] THIRD = 2'b10;
parameter [1:0] FOURTH = 2'b11;


always @(posedge clk or posedge rst) // sequential
begin
if (rst) state <= FIRST;
else state <= next_state;
end

always @* // combinational
begin
case (state)
FIRST: if (invalid | insufficient_fare) next_state = FIRST;
else next_state = SECOND;
SECOND: if (invalid | insufficient_fare) next_state = FIRST;
if (prepaid) next_state = THIRD;
if (unlimited) next_state = FOURTH;
THIRD: if (prepaid) next_state = FOURTH;
default: next_state = FIRST;
endcase
end
endmodule

when trying to compile:

** Error: C:/Users/Keith/Desktop/subway turnstile fsm project/WORKS1turnstile_subway.v(31): near "if": syntax error, unexpected if
** Error: C:/Users/Keith/Desktop/subway turnstile fsm project/WORKS1turnstile_subway.v(33): near ":": Syntax error. Statement labels are only allowed in SystemVerilog.


Again any insight is greatly appreciated.

 

You need to write your code in a structured way and make the presentation match the structure. Look at your references for the preferred ways to present your code. That will make tracking down the errors much easier.

Also, the error messages provide line numbers as hints. But they aren't very helpful to us when we don't know what lines are what number.