fsm design problem in output decoder

Discussion in 'General Electronics Chat' started by limbonic, Oct 29, 2012.

  1. limbonic

    Thread Starter New Member

    Jul 4, 2011
    Hello, i try to design the output decoder of the above FSM and i stuck in the process.

    The state diagram:


    i make the VEMs according to the above diagram (x1,x2,x3,x4,x5 is outputs):


    My problem is that i dont know how to design the output decoder when for example x3 signal equation contains x4 signal and x4 signal equation contains x3 signal.
    Anyone can help me?
    Thanks :)
    Last edited: Oct 29, 2012
  2. BillO

    Distinguished Member

    Nov 24, 2008
    It has been some time since I studied finite sate machines, but I can't make much out of the information you have given.

    • What do you mean 'above FSM'?
    • There are 5 states shown, not 3
    • Are the outputs (X1 to X5) supposed to be Moore or Mealy?
    • What causes the transition from the state 010 to the state 011?
    • Why is a state labeled 111 when there are no states 100, 101 and 110?
    • Your variable entry maps (VEM) don't look right, but I've never used Ptolemy so take that for what it's worth.
    • Can you give us the full original question and all the information that goes with it?
    From what I remember, states do not depend on outputs. Rather, states depend on either inputs, or inputs and previous states. Outputs can depend only on state (Moore outputs) or on state and input (Mealy). So outputs occur when you are in a particular state or when you are in a particular state and a specific input occurs, but they do not drive states or state changes.
    Last edited: Oct 29, 2012
  3. kubeek


    Sep 20, 2005
    What are those d´s in the karnaugh maps? Why is the input D from the state diagram not included in the map?