# Frequency vs voltage

#### sara83

Joined Jul 5, 2021
2
Hi,
Suppose I have an ASIC which runs at 4Ghz clock and at a particular voltage... I increase the frequency to 6Ghz....why do I have to increase the voltage.... ?? can someone please explain the relationship between frequency and operating voltage... ??

Thanks!
Satish.R

#### bertus

Joined Apr 5, 2008
21,760
Hello,

Have a look at the datasheet of the ASIC.
Is the ASIC able to run at 6 GHz?
A higher clock frequency will likely produce more heat.

Bertus

#### Papabravo

Joined Feb 24, 2006
17,528
I'm not familiar with anything that would lead in that direction. There is a relationship between power supply voltage, switching frequency, and power dissipation. One reason for reducing the internal voltage on an ASIC is that power dissipation is proportional to the square of the power supply voltage. That would seem to argue for a reduction in the power supply voltage as the switching frequency increases.

Power Consumption - Semiconductor Engineering (semiengineering.com)

#### eetech00

Joined Jun 8, 2013
2,762
In general, a higher clock speed will require faster rise times and shorter delays for internal components. Capacitive charge times will have to be faster, thus higher voltages are sometimes required to reach faster clock speeds.

#### ronsimpson

Joined Oct 7, 2019
1,750
I know this is not ASIC but it is CMOS 15V logic. CD4020 The time to do this function at 5V is 200nS, 10V=80nS and 15V=60nS. I have run these at 3V and they are very slow. I have also used these with a heat sink on top at 20V and they are faster yet. (some do not survive)

There are many micro-computers with a graph of speed verses supply voltage.

#### dl324

Joined Mar 30, 2015
13,809
Welcome to AAC!
can someone please explain the relationship between frequency and operating voltage... ??
Gate delay decreases linearly with increased voltage, but power dissipation increases quadratically.

#### Papabravo

Joined Feb 24, 2006
17,528
Welcome to AAC!
Gate delay decreases linearly with increased voltage, but power dissipation increases quadratically.
The traditional tradeoff to compensate for the reduction in power supply voltage is to make the features smaller. When they can't get any smaller, you must increase the power supply voltage and deal with the power dissipation issue by using, for example, cryogenic cooling methods. The expense of that could not be justified in earlier semiconductor generations, but for now we are outa' gas on making things smaller. The boiling point of Liquid Nitrogen is 77 °K, LOx is 90 °K. That plumbing will require some serious expense.

#### dl324

Joined Mar 30, 2015
13,809
Increased power dissipation means more heat. More heat means more stress on the conductors (from electromigration and/or self-heat) and transistors.

When you operate a device at higher frequency you can run in to speed paths that will cause malfunction.

#### dl324

Joined Mar 30, 2015
13,809
but for now we are outa' gas on making things smaller.
Manufacturers are working on nodes at 3nm and smaller. Current production devices are around 5-7nm. Not quite out of gas yet.

#### Papabravo

Joined Feb 24, 2006
17,528
Manufacturers are working on nodes at 3nm and smaller. Current production devices are around 5-7nm. Not quite out of gas yet.
Close enough so previously unfathomable alternatives are suddenly being considered.

#### dl324

Joined Mar 30, 2015
13,809
Close enough so previously unfathomable alternatives are suddenly being considered.
The "end" has been predicted many times over the past couple decades. I remember a colleague who was a recently minted process guy telling me that 10nm was the "end". This was in the mid to late 90's and we were trying to get 250nm to production at the time.

By inventing strained silicon, using multiple patterning, inventing fin FETs, EUV litho, and many other things, the end has been pushed out decades. Every time somebody predicts the end, they've been proven wrong by the people who do that stuff for a living.

For most of us, process technology is a don't care. I'm writing this on a laptop using a first generation i3 that I bought in 2010 and it's still sufficient for all of my needs. I don't care that it's a 32nm design. I'd like a faster computer, but I don't really need one. What I really want is a Windows operating system that does what it's supposed to do.

#### Deleted member 115935

Joined Dec 31, 1969
0

To a first degree ,

the threshold of a "logic blocks" is almost constant despite voltage,
Whilst a "logic block" output voltage is dependent upon voltage,

So as the voltage increase, the time it takes for the input threshold to be reached decreases as the voltage increases.

#### sara83

Joined Jul 5, 2021
2
It's something got to deal with the heat... can someone explain the relationship between heat generated ,operating voltage and frequency.... ??

#### Papabravo

Joined Feb 24, 2006
17,528
It's something got to deal with the heat... can someone explain the relationship between heat generated ,operating voltage and frequency.... ??
The link in Post #3 lays out the connection between voltage, frequency, and power consumption. Power consumption is associated with a rise in temperature. Most IC's have a parameter called thermal resistance expressed in °C/Watt. So you take this number, multiply it by the power dissipation for the device and it will give you an estimate of the temperature rise.

#### michaeltimmermann1

Joined Jun 28, 2021
1
Applied voltage has a relative to slew rate. So, in this case, greater voltage may be a way to get faster slew rate. On the other hand, the greater voltage brands a greater distance to travel between source rails. This spreads the travel time, so do we increase or lose? Not sure.