Frequency Doubler Technique Request

Thread Starter


Joined Feb 22, 2007
Attached is a drawing of a frequency doubler that works in simulation.
Pulse width is approximately 0.693*R*C

Hope this helps
Hey there, im really interested in this frequency doubler schematic, i need to asemble a similar application. If can send it to me that'll be great



Joined Feb 24, 2006
I posted it on the forum. Its just an XOR gate with a single pole RC filter on one of the inputs. There is a pulse for each edge of the original signal and the value of R an C controls the pulse width based on the threshold of the gate in question. CMOS gates normally have their threshold set at Vdd over 2