Hi,

I'm having a bit of trouble trying to figure out frequency divisions in counter circuits.
For example, in a 7492 counter the clock inputs CP0 and CP1 receive a signal with a certain equal frequency ƒ , will all the outputs Q0,Q1,Q2,Q3 be half the input frequency?
or does it get devided independently at each output? i.e Q0=1/2ƒ, Q1=1/4ƒ, Q2=1/8ƒ, etc? Please help me clarify this. Thank you.

 

Originally posted by leyb@Dec 5 2005, 06:51 PM
Hi,

I'm having a bit of trouble trying to figure out frequency divisions in counter circuits.
For example, in a 7492 counter the clock inputs CP0 and CP1 receive a signal with a certain equal frequency ƒ , will all the outputs Q0,Q1,Q2,Q3 be half the input frequency?
or does it get devided independently at each output? i.e Q0=1/2ƒ, Q1=1/4ƒ, Q2=1/8ƒ, etc? Please help me clarify this. Thank you.

[post=12207]Quoted post[/post]​

You are correct; each suceeding stage is divided by two from stage input to output for a 7493. Q0 needs to be wired to CP1 to cascade that stage to the others, which I believe are cascaded by internal wiring

Keep in mind that the 7492 is a 1/12 counter, the first stage is 1/2, the last three stages have feedback to divided by 6. So overall divide by 12 if Q0 is cascaded to CP1

You did not ask about this about a 7490 counter which has a 1/2 stage followed a 1/5 stage for 1/10 overall when Q0 is cascaded to CP1. The last three stage have feedback to force 1/5 as opposed to 1/8 for no feedback.

 

Got it. Thanks