Iam working on tranistor level (couse after this ill do the IC layout) frequency divider and i met some problems. I started of simple divider by 2 (D flip flop with Qnot wired into D). No matter what type of d flip flop iam making (NAND gates or Transmision Gate) i dont get desired output... I would appreciate any help.

 

We are not mind readers. How do you expect us to help you figure out what is wrong with your design when you don't show us your design? You don't even tell us what output you are actually getting.

 

Have you checked the datasheet for the CD4013? It includes a schematic of the IC internals.

 

Did you connect and turn on the power?

 

Did you connect and turn on the power?

It sounds like just a circuit design at this point that is then going to be laid out as if it were going to be fabbed as an IC.

 

Pasting LTspice schematic + simulation:

Schematic of Transmission Gate based Dff.

 

The default FET models don't give realistic results. Choose specific FETs.

 

With model

 

I have a question about making IC layout and I dont want to make a new thread... So lets supose that my goal is to make W=1u L=1u channel transistor. Is it any diffrence if I use technology with lambda=0.2u (so transistor is 5x5 lambda) or technology with lambda=0.5 (so transistor is 2x2 lambda)?

 

I think I can see your problem. Let's see if I can get you so see your problem.

Whenever a circuit isn't doing what you think it should, you need to delve into it and see exactly what it IS doing. All you appear to have done is shown that your circuit isn't giving the signal behavior you want and then given up and come here (and I'm sure that this is an exaggeration, so please don't take offense). Instead, take a step back and see if your circuit functions as a normal DFF and what its parameters are like. To do this, break your Q'->D connection and apply an external signal to D. Then display the signals at all of the data path nodes of the DFF and be sure that you understand them and agree with them. If they don't look good, then the problem is with your underlying DFF design. A transmission gate based design is pretty sensitive to gate sizes and clock edge locations.

Once you know the DFF works, then make your D signal match your Q' signal (by changing the D signal, not by connecting them together) and see if you reproduce the incorrect results. If you do, then play around with the D signal to determine where the behavior goes bad.

 

I have a question about making IC layout and I dont want to make a new thread... So lets supose that my goal is to make W=1u L=1u channel transistor. Is it any diffrence if I use technology with lambda=0.2u (so transistor is 5x5 lambda) or technology with lambda=0.5 (so transistor is 2x2 lambda)?

If you are talking about using scalable rules, then to a first approximation it makes no difference. That's the point of scalable rules. In practice, particularly in modern processes, scalable rules prevent you from achieving the best layout and performance because of the need to meet all of the design rules with a single scaling parameter.

 

I found an error!!! Dff is working as expected. Problem was simple, I didnt know that i need to connect transmission gates transistors Body pin to Vdd (for PMOS) and Gnd (for NMOS) because i red somewhere that Body pin is always shorted to the Source pin...

Yeah conecting D with Qnot doesnt work for divider. Can u clarify what u mean
by: "make your D signal match your Q' signal (by changing the D signal, not by connecting them together)" ???

PS: I was checking if its working as a normal Dff and it wasnt. I am not kind of person that wrotes on forums couse he is lazy to test on his own.

 

I found an error!!! Dff is working as expected. Problem was simple, I didnt know that i need to connect transmission gates transistors Body pin to Vdd (for PMOS) and Gnd (for NMOS) because i red somewhere that Body pin is always shorted to the Source pin...

Yeah conecting D with Qnot doesnt work for divider. Can u clarify what u mean
by: "make your D signal match your Q' signal (by changing the D signal, not by connecting them together)" ???

PS: I was checking if its working as a normal Dff and it wasnt. I am not kind of person that wrotes on forums couse he is lazy to test on his own.

The body is connected to the source in discrete packages. In ICs, the designer has the option of where to connect the body wells. For digital logic they are usually connected to supplies so that you can put multiple transistors in the same well even if their sources are not connected together.

What I meant was, for testing purposes, so use an independent signal source that mimicks Qnot. This allows you to move it back and forth relative to the clock edges to explore your setup and hold times. On issue that is often encountered with modern processes is that the propagation delay is so short that the signals race the clock and win, thus violate the timing constraints.

Also, a good practice to get into is to run all of your signal sources through buffers that are close to what would be on the chip so that they have realistic rise and fall times as well as drive strength.

PS: You need to get over the being lazy part. You are training to become an engineer, which is someone that solves other people's problems. You will have value to your employer only to the degree that you are able to do that. Certainly you will work with others on things and certainly you will encounter things where you need to seek assistance, but the more you learn to explore problems and seek solutions on your own, the more valuable you will be to your employer and coworkers.

 

Much progress today. I have design requirements for power consumption and to measure it I simply plot Vcc*Icc and power consumption is average value (alt+ctrl+left click plot name)?