In the past we had to create a AND-OR 3 bit parity generator/checker. But im not sure how to do the 7bit. I think I have to use MUX. How would I go about designing it? Do I need a truth table? Im kind of lost. I just need a sense of direction on how to go about doing this. He gave us a state diagram
Also this is the assignment
Also this is the assignment
Experiment 7 - FPGA state machine implementation of a simple sequential odd parity generator/checker for a 7 bit memory
Design a state machine implementation of a simple sequential 7 bit odd parity generator/checker system that performs as follows.
Use a reset button (BTN0) to intialize the system such that the bits of data register R (R7-R0) and data register S (S7-S0) are 0 and all eight LEDs are initially unlit.
Pushbutton BTN1 is used to load one of the registers from switches SW7 - SW1 (LSB). The register to be loaded is selected using SW0. If SW0=0 when pushbutton BTN1 is pushed, then 7 data bits are loaded from switches SW7 - SW1 (LSB) to the corresponding bits of register R. If SW0=1 when pushbutton BTN1 is pushed, then 7 data bits are loaded from the switches to the corresponding bits of register S.
Pushbutton BTN2 is used to check parity for the register selected using SW0. If SW0=0, parity is checked for R. If SW0=1, parity is checked for S. When pushbutton BTN2 is pushed the parity for the selected register is generated using a sequential parity checker, and the parity bit is stored in bit 0 of the selected register. Once the parity check is complete, the contents of the register are displayed using LED7-LED0 corresponding to register bits 7 through 0, with the LED lit if the register data is a 1.
See the following file (Blackboard) for some examples of the types of Xilinx building blocks that might be useful in this experiment.
Xilinx mux, D flip flop, shift register components.pdf
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